Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Timmah!]

For guys like MLID and Charlie, it's a mistake to take their word as gospel, but it's also a mistake to discount them entirely.

Agreed.

The only issue i personally have with these guys is their constant need for approval of their self-importance. Like the recent Adored video on Zen4 posted here, only second half the video concerns the actual Zen 4, the first half is completely all about "remember when i told you this and that and see how right i was". MLID does the same. Its annoying and gets old really quickly. One would think they design or produce those CPUs/GPUs themselves based on such attitude. I do appreciate their content for entertainment purposes, but it would be nice, if they realized thats all what is there to them and toned it down a bit.

 

[RTX2080]

my feeling about rumors```

AMD hide their secrets soooo well these years, and those leakers produced sooo much hilarious rumors. "5Ghz Zen2" is the one of those.
When I saw the 5.85Ghz(Fmax) rumor and expectations of 6Ghz+ by some guys, I realize that the speculations are completely off the rails again.
These years AMD gave me an impression, that they just did what they have scheduled during Zen1 design timeframe, and they couldn't do any other aggressive things which are not in the schedule. If they wanna develop other ways, they would have warned us.
So many "leakers" got slap in the face before, this time I'm afraid they would again be slapped.

In detail, I don't know how I could trust the "5.85Ghz" source, but last days I knew is that AMD didn't even got the qualification sample to test before-during Computex. So this rumor is quite suspicious for me. At least it is more like a guess than a "source" exist.

 

[Henry swagger]

Agreed.

The only issue i personally have with these guys is their constant need for approval of their self-importance. Like the recent Adored video on Zen4 posted here, only second half the video concerns the actual Zen 4, the first half is completely all about "remember when i told you this and that and see how right i was". MLID does the same. Its annoying and gets old really quickly. One would think they design or produce those CPUs/GPUs themselves based on such attitude. I do appreciate their content for entertainment purposes, but it would be nice, if they realized thats all what is there to them and toned it down a bit.

They make big money from it. So they like spicing things up

 

[Mopetar]

The switch to 5 nm may allow them to keep good latencies while increasing clock speeds. I don’t expect some massive pipeline reorganization between Zen 3 and Zen 4. Rebalancing pipeline stages is a lot of work. Zen 5 might be drastically different though.

Zen 4 seems like a die shrink for the most part. The only major changes are increasing the L2 cache size (seems like they doubled the number of sets) and adding AVX-512 support. The IO die getting built-in graphics is also a pretty big deal. There's a lot of work that has gone into Zen 4, but it's just not the same parts that we saw during the transition from Zen 2 to Zen 3.

From the AT interview with Mike Clark last fall, I get the impression that Zen 5 is more of a fresh design. Mike doesn't outright say what's changing, but the conversation topics do hint at it. He also states that their high-level design approach is to create a grounds up redesign, then a derivative of that to improve on it, but that because a second derivative doesn't have as much room for improvement, to start with a new fresh design based on lessons learned.

From this we should expect that Zen 5 may have some radical design changes. I'm expecting that the front-end will have seen some serious work, because it's difficult to keep making a wider design with more execution units if you can't keep them all fed.

 

[biostud]

Zen 4 seems like a die shrink for the most part. The only major changes are increasing the L2 cache size (seems like they doubled the number of sets) and adding AVX-512 support. The IO die getting built-in graphics is also a pretty big deal. There's a lot of work that has gone into Zen 4, but it's just not the same parts that we saw during the transition from Zen 2 to Zen 3.

From the AT interview with Mike Clark last fall, I get the impression that Zen 5 is more of a fresh design. Mike doesn't outright say what's changing, but the conversation topics do hint at it. He also states that their high-level design approach is to create a grounds up redesign, then a derivative of that to improve on it, but that because a second derivative doesn't have as much room for improvement, to start with a new fresh design based on lessons learned.

From this we should expect that Zen 5 may have some radical design changes. I'm expecting that the front-end will have seen some serious work, because it's difficult to keep making a wider design with more execution units if you can't keep them all fed.

Tick-tock

 

[RTX2080]

Tick-tock

No more tick-tock because MOORE'S LAW IS DEAD

 

[TESKATLIPOKA]

I really don’t know why I find your “AMD is sacrificing power efficiency for performance” so ridiculous, but I do, so I guess I still have to try to write a reply.
Zen 4 will be significantly more power efficient than Zen 3 just about anyway you look at it. They are increasing the power limits since they will have a lot higher max all core clock, but it isn’t like that doesn’t deliver significantly more performance. I expect it will be a large difference in many cases. Base clock for the 5950x is only 3.4 GHz; I think someone said they can run all core at 3.7, presumably without extreme cooling. If Zen 4 does all core over 5 GHz, the performance will be truly amazing in comparison.

I bring up overclocking because no matter what clock speed you compare, Zen 4 will almost certainly be more efficient. If you compare the same performance, then Zen 4 will likely be significantly more efficient everywhere also. They probably did a lot of power optimization on the IO die, so I expect idle power is significantly improved.

1. I never said Zen4 will be less (power) efficient than Zen3 at the same TDP(PPT).
2. I never said Zen4 will be less (power) efficient than Zen3 at the same clockspeed.
2. I never said Zen4 will be less (power) efficient than Zen3 at the same performance.
3. You don't need to explain to me why AMD increased the power limit to TDP: 170W(PPT: 230W). I already knew the reason.
4. I said 16C32T TDP: 170W(PPT: 230W) Zen4 based CPU(7950x?) could be less (power) efficient in MT than a 16C32T Zen3 based 5950x TDP:105W(PPT: 142W) unless It can increase the performance by the same amount as the TDP(PPT) increased and that is ~62%.

So what if your absolute performance per watt might be slight lower at extreme clocks, but absolute performance is something like 40 percent higher or more? I do not consider this worse power efficiency; it is in a range that Zen 3 can’t reach without taking ridiculously more power.
Saying that they are sacrificing efficiency seems misleading at best. If they are pushing Zen 4 significantly farther up the frequency / power curve, where you get huge increase in power for a small increase in performance, then I would say they are sacrificing efficiency. We don’t have any evidence that they are doing that. They are increasing the max power, but that appears to be coming with a reasonable increase in performance for that power. It isn’t unexpected with a new socket after so many years of AM4.

If the power consumption of a CPU increases by ~62% but absolute performance only by 40% for example, then It will have worse power efficiency and I don't see a problem in saying "AMD sacrificed power efficiency for performance" with this CPU model.
It's not important If Zen3 is capable of such clockspeed or at what power consumption, because I compared them at their stock settings. The reviewers will do a similar comparison. Will you criticize them for that?

I don't understand what's your problem with what I wrote.
So what If this CPU will end up with worse power efficiency than It's predecessor. It will also be a lot faster. It's a good tradeoff in my opinion. If someone wants a more efficient Zen4 CPU like me, then just choose one with lower TDP(PPT) or a laptop model. It's so simple.

 

[Schmide]

Zen 4 seems like a die shrink for the most part. The only major changes are increasing the L2 cache size (seems like they doubled the number of sets) and adding AVX-512 support.

That's kindo contradictory. Doubling the L2 and adding a buncho instructions is a fair amount of work, with the improved performance hinting at various changes, I think it's best not the quantify it as such.

Edit: + ddr5 + pcie5 + GPU + etc

 

[Abwx]

If the power consumption of a CPU increases by ~62% but absolute performance only by 40% for example

With their customised N5 they can get the same perf at 0.5x the TDP with no IPC improvement.

At 10% higher MT IPC they could have 30% more perf at same TDP, so at 170W PPT they can get another 10% on top of said 30%.

 

[jpiniero]

With their customised N5 they can get the same perf at 0.5x the TDP with no IPC improvement.

At what clock speed though.

 

[Mopetar]

Tick-tock

Basically that idea. It seems like AMD hasn't been as stagnant as Intel with their iterations though. Intel may have made some changes under the hood or tried out some interesting ideas such as the L4 eDRAM cache, but their designs almost always felt more incremental. Perhaps some of that can be attributed to their process node woes and needing to scrap or redesign products time and time again, but without Zen it's not hard to imagine a 12700K with the same 4 cores they were content to sell year after year.

 

[biostud]

Basically that idea. It seems like AMD hasn't been as stagnant as Intel with their iterations though. Intel may have made some changes under the hood or tried out some interesting ideas such as the L4 eDRAM cache, but their designs almost always felt more incremental. Perhaps some of that can be attributed to their process node woes and needing to scrap or redesign products time and time again, but without Zen it's not hard to imagine a 12700K with the same 4 cores they were content to sell year after year.

tick-tock was, new design - > new process node -> new design ... not: slight design change -> process node+ -> slight design change -> proces node++

 

[Mopetar]

That's kindo contradictory. Doubling the L2 and adding a buncho instructions is a fair amount of work, with the improved performance hinting at various changes, I think it's best not the quantify it as such.

Edit: + ddr5 + pcie5 + GPU + etc

Yes and no. The move from Zen 2 to Zen 3 saw a big jump in performance in the areas that most casual users care about.

Zen 4 isn't going to be as exciting for those users, but if you have an AVX-512 workload then Zen 4 is big for you. From comparisons between using DDR4 and DDR5 in Alder Lake there are a few applications that get a substantial performance boost from the additional memory bandwidth. For users of those applications Zen 4 is a major uplift.

Frankly I don't get why some people seem so disappointed with it. Even if the IPC gains aren't substantial, AMD is getting a big uplift in clock speeds. We've seen it can do at least 5.5 GHz already and there are some rumors that peg the max at 5.85 GHz. A 5800X had a boost of 4.7 GHz. If we get a 6800X with 5.5 GHz that's a 17% bump without considering any IPC uplift. We already know that some games see performance uplift from DDR5 and that additional cache makes a slower clocked Zen 3 CPU substantially faster. If you add another 5% performance from the cache an another 5% for DDR5, suddenly that's a 30% uplift over Zen 3 for that same game.

 

[JoeRambo]

Frankly I don't get why some people seem so disappointed with it. Even if the IPC gains aren't substantial, AMD is getting a big uplift in clock speeds.

The only people who are dissapointed are the crowd who bought the baseless leaker tales about "massive IPC increase". I am very looking forward to Zen4 as long as they don't pull another 5800X3D with locked voltage and frequency controls. Damage to chip efficiency by marketing retards is easy to undo by underclocking and undervolting, so moving from 4.4Ghz 5950x to near 5Ghz 7950x sounds perfectly viable to me. Sounds like at least 20% perf win at same efficiency. Could be bigger in my workloads due to 1MB of L2 and DDR5. Fine with me.

 

[Schmide]

Yes and no. The move from Zen 2 to Zen 3 saw a big jump in performance in the areas that most casual users care about.

Zen 4 isn't going to be as exciting for those users, but if you have an AVX-512 workload then Zen 4 is big for you. From comparisons between using DDR4 and DDR5 in Alder Lake there are a few applications that get a substantial performance boost from the additional memory bandwidth. For users of those applications Zen 4 is a major uplift.

Frankly I don't get why some people seem so disappointed with it. Even if the IPC gains aren't substantial, AMD is getting a big uplift in clock speeds. We've seen it can do at least 5.5 GHz already and there are some rumors that peg the max at 5.85 GHz. A 5800X had a boost of 4.7 GHz. If we get a 6800X with 5.5 GHz that's a 17% bump without considering any IPC uplift. We already know that some games see performance uplift from DDR5 and that additional cache makes a slower clocked Zen 3 CPU substantially faster. If you add another 5% performance from the cache an another 5% for DDR5, suddenly that's a 30% uplift over Zen 3 for that same game.

I am not disappointed at all.

AVX-512 alone is a large rework. The system now has to swizzle data across 4 lanes, provide gather instructions, mask instructions, fp16, etc.

Even if there was a regression in performance, it has far to many changes to even slightly categorize it as a die shrink. It's a new socket, new IO die, new heat spreader, new power target.

I can't think of any other new platform that has such weird nomenclature attached to it right out of the gate.

 

[Abwx]

At what clock speed though.

0.5x the power at 4GHz on Cinebench...

They can get to 4.8GHz at same power, or at least within 142W PPT since the 5950X doesnt reach this value in this bench, at 170W PPT they can get up to 5GHz.

The 230W PPT is related to the plateform power upgrade, up from AM4 142W, certainly due to future products including a big GPU chiplet with more than 1024 SPs.

 

[jpiniero]

0.5x the power at 4GHz on Cinebench...

They can get to 4.8GHz at same power, or at least within 142W PPT since the 5950X doesnt reach this value in this bench, at 170W PPT they can get up to 5GHz.

Don't think it works that way. AMD saying 0.5x doesn't mean it will stay that way all up the V/f curve.

 

[Abwx]

Don't think it works that way. AMD saying 0.5x doesn't mean it will stay that way all up the V/f curve.

That s why i said 4.8Ghz, that is 20% higher while they state 25% higher for more favourable parts of the curve, i also stated within 142W because the 5950X is at 125W@4GHz on Cinebench.

All in all that seems doable to be within 5GHz@170W considering those numbers, probably that they gave up a little on density to achieve higher frequencies, that explain the similarly sized chiplet despite a theorical 1/0.6x density improvement for N5 vs N7.

 

[moinmoin]

Tick-tock

For the Zen cores I'd call it the redesign -> expansion cycle: Zen 1 was a redesign, Zen 2 an expansion of that, Zen 3 a redesign, Zen 4 an expansion of that.

For the uncore it seems the expansion step is used to redesign the I/O: Zen 2 brought use the IOD, which Zen 3 reused, Zen 4 brings us an efficiency optimized IOD including an iGPU.

Process node changes are more muddy, though the expansion step so far was used to switch the node family as well: Zen and Zen+ on GloFo 14/12nm, Zen 2, 3 and 3+ on TSMC N7 and N6. Zen 4 and 5 on N5 and N4, Zen 6 on N3?

 

[RTX2080]

For the Zen cores I'd call it the redesign -> expansion cycle: Zen 1 was a redesign, Zen 2 an expansion of that, Zen 3 a redesign, Zen 4 an expansion of that.

Although I have doubts on redesign or expansion explanation, I believe the Zen would be one step forward by each generation, unless AMD warn us they have to totally change the plan.

I guess Zen4 would be no surprise if you compare to older generations, double digit IPC and single digit clocks, both would not be exaggerated like 20%,30%, this changes exceed AMD/TSMC's ability.

well, I would leave more comments if I still interested in this guesstimation topic but there's still too little information to refer to, so that I would rather wait and silent``````

 

[DisEnchantment]

Zen 4 seems like a die shrink for the most part. The only major changes are increasing the L2 cache size (seems like they doubled the number of sets) and adding AVX-512 support. The IO die getting built-in graphics is also a pretty big deal. There's a lot of work that has gone into Zen 4, but it's just not the same parts that we saw during the transition from Zen 2 to Zen 3.

Not really a die shrink, based on known Linux patches alone, Zen4 seems like a big change in many areas besides AVX512.
L3 block heavily redesigned to support new RAS features, new PMU and new IBS

Linux 5.19 Perf Changes Bring Three Notable AMD Features - Phoronix

www.phoronix.com

AMD SMCA Updates Land In Linux 5.17 For Future CPUs - Phoronix

www.phoronix.com

MPDMA hints also present in SMCA patches

L2 is doubled
L1 and L2 DTLB increased. Dual SDP ports

Details on the Gigabyte Leak

Recently, a ransomware group leaked data from Gigabyte in an attempt to extort payment.

chipsandcheese.com

UAI

AMD Posts New Linux Code For Zen 4's UAI Feature - Phoronix

www.phoronix.com

57 bit addressing

AMD Preparing 5-Level Paging Linux Support For Future CPUs - Phoronix

www.phoronix.com

IOD is a massive overhaul which needs no introduction, CXL, DDR5, IF3.0, PCIe5, NVDIMM-P, out of box Cache coherent interconnect, etc etc

Frankly I don't get why some people seem so disappointed with it. Even if the IPC gains aren't substantial, AMD is getting a big uplift in clock speeds. We've seen it can do at least 5.5 GHz already and there are some rumors that peg the max at 5.85 GHz. A 5800X had a boost of 4.7 GHz. If we get a 6800X with 5.5 GHz that's a 17% bump without considering any IPC uplift. We already know that some games see performance uplift from DDR5 and that additional cache makes a slower clocked Zen 3 CPU substantially faster. If you add another 5% performance from the cache an another 5% for DDR5, suddenly that's a 30% uplift over Zen 3 for that same game.

You can blame AMD's messaging for the disappointment.

AMD has been throwing shade about the competitor IPC increases and also about how bloated the competitor core is. Interviews with Taylor/Hallock, and Hallock on the Zen3+/6000 release and probably more than what I would have watched.
Going by the DerBauer's video for the Zen4 CCD of ~70mm2 there is a massive >50% MTr even with a modest 90MTr/mm2 (compared to >134MTr/mm2 for Apple chips).
>50%... this is a gigantic gain in MTr (Zen3 is like 9% gain in MTr),
Imagine 50 percent more transistors for a measly single digit gain in performance per clock. I doubt you'd be impressed if you are being honest. The frequency and efficiency gains are for the most part TSMC's achievements, not AMD's.

While I will reserve my disappointment/opinion/etc on Zen4 core until the launch, the messaging is not very consistent, which is not inspiring confidence and therefore all this discussion we are having.
However I will not deny that I enjoyed seeing some AMD evangelists squirming with the reveal

That being said, however there could be more than what Hallock is allowed to reveal.
They cannot just throw around 2 million additional transistors doing nothing. I feel there could be a lot more INT improvements than FP this time around but we shall see.

 

[JoeRambo]

Going by the DerBauer's video for the Zen4 CCD of ~70mm2 there is a massive >50% MTr even with a modest 90MTr/mm2 (compared to >134MTr/mm2 for Apple chips).
>50%... this is a gigantic gain in MTr (Zen3 is like 9% gain in MTr),

Some of it is burned by enlarged L2 and a lot went into AVX512 support. It requires 3-4x area for FP PRF ( double the bits and double architectural registers and the rest of PRF just doubled bits ) and execution units are massive as well, requiring a lot of varied logic. Does not come free, esp considering this is their first AVX512 implementation, so logic implementation might not be as tight as Intel's.

 

[DisEnchantment]

Some of it is burned by enlarged L2 and a lot went into AVX512 support. It requires 3-4x area for FP PRF ( double the bits and double architectural registers and the rest of PRF just doubled bits ) and execution units are massive as well, requiring a lot of varied logic. Does not come free, esp considering this is their first AVX512 implementation, so logic implementation might not be as tight as Intel's.

If they burnt 50% more MTr and a huge chunk of silicon real estate (and wafer costs) for a few niche AVX512 workloads then investors should be really really worried about their GMs.
I doubt the bean counters will let this slide.

 

[HurleyBird]

If they burnt 50% more MTr and a huge chunk of silicon real estate (and wafer costs) for a few niche AVX512 workloads then investors should be really really worried about their GMs.
I doubt the bean counters will let this slide.

If they did, they did it for the sake of the server market, not for desktops.

AMD is already dominating Intel in most server workloads. Adding even more cores would let AMD dominate those workloads a bit more, but Intel would still have the AVX 512 niche all to themselves.

But we don't know all the factors. It's also possible that AMD made a purposeful density tradeoff to chase clock speeds. Maybe the new CCX design is inflexible and doesn't scale well past 8 cores. And of course, there's also Zen4C which is density focused already. It makes sense that if you have two types of CCDs and one is density focused, that the other is the opposite.

 

[leoneazzurro]

If they burnt 50% more MTr and a huge chunk of silicon real estate (and wafer costs) for a few niche AVX512 workloads then investors should be really really worried about their GMs.
I doubt the bean counters will let this slide.

Imagine Intel having done the same in ADL and not even enabling it for desktop...