Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[PJVol]

That s not 146W.

That's exactly what it reports - 146W. But...
1) his cpu is not at stock, since RM clearly shows OC mode is on, hence 103% PPT and 114% TDC.
2) 110W is what both CCDs are consuming, i.e. core logic, cache, etc.
3) As for TDP, I have no idea why this stupid metric even exists. And I can't recall a single occurance of it being used in a Zen power management.

 

[eek2121]

It is possible that Zen 4 could have nearly a 20% (single core) frequency increase over Zen 3 if that article is correct.

That's exactly what it reports - 146W. But...
1) his cpu is not at stock, since RM clearly shows OC mode is on, hence 103% PPT and 114% TDC.
2) 110W is what both CCDs are consuming, i.e. core logic, cache, etc.
3) As for TDP, I have no idea why this stupid metric even exists. And I can't recall a single occurance of it being used in a Zen power management.

TDP has nothing to do with power.

 

[Abwx]

Please enlighten us if 110W includes SOC power and not. And if it does, please provide your "math" how 103% of whatever your calculations includes 110 + 23W of SOC?

Hint, Ryzen Master tooltip for "110W" part of Your calculations looks like this:
View attachment 62316

And just look how Package Power is described in HwInfo64 ( and how closely estimate is tracking PPT ):
View attachment 62317


So for anyone not using troll level of math, I will repeat:

Mark's CPU is using 146W (142W*1.03) of power at the socket, that is the value that is comparable to PL1/PL2 limits long term for Intel's CPUs and not what is indicated in "CPU-POWER" field there.
AMD is rising 142W value to 230W, so they will have 60+% of extra power to play with in certain SKUs.

But he didnt display anything from HVInfo, all numbers are from RyzenMaster, and his 110W make sense since the CPU run at 3.7GHz only, as said Computerbase measure 125W@4GHz (with CB), wich correlate with Mark s numbers.

FTR the CPU cant get above 142W unless PBO is enabled, wich will remove the 142W limitation.

That being said what would definitively set the debate is a measurement at the wall when idling and then at his full loading.

That's exactly what it reports - 146W. But...
1) his cpu is not at stock, since RM clearly shows OC mode is on, hence 103% PPT and 114% TDC.
2) 110W is what both CCDs are consuming, i.e. core logic, cache, etc.
3) As for TDP, I have no idea why this stupid metric even exists. And I can't recall a single occurance of it being used in a Zen power management.

PPT is at 142W and is 135% of the TDP.

When 103% is displayed it means that the CPU is at 103% of its rated TDP, if it reach 142W then 135% is displayed.

 

[JoeRambo]

But he didnt display anything from HVInfo, all numbers are from RyzenMaster, and his 110W make sense since the CPU run at 3.7GHz only, as said Computerbase measure 125W@4GHz (with CB), wich correlate with Mark s numbers.

Look, You were already told multiple times, that with or without HWINFO64, his package power is 146W, it is shown as 103% of 142W PPT. 110W as displayed in Ryzen Master is cores only power value.
No need to invent things.

When 103% is displayed it means that the CPU is at 103% of its rated TDP, if it reach 142W then 135% is displayed.

That is not how it Ryzen Master works. 142W will show 100% of PPT, lets not invent bs theories. Just like percentages in EDC, TDC etc track their own.

 

[coercitiv]

TDP has nothing to do with power.

AMD TDP has less to do do with power and more to do with recommended heatsink properties, Intel TDP is literally a package power limit.

Saying TDP has nothing to do with power was the way this forum handled discussions with people who were unable to understand the dynamics of CPU power draw and thus introduced an overwhelming amount of noise in all TDP related discussions, be it for AMD or Intel. So they told them that TDP isn't power to get some peace and quiet.

But those times are long gone, now we can't even agree what a 103% gauge means when the label is clearly written bellow, including the numerical value for 100%

 

[igor_kavinski]

Better than what? Intel's Comet Lake DDR4 controller could hit latency like that. So could Coffee Lake.

I was comparing latency of eDRAM to that of DDR5. ADL with DDR5-4800 could have benefited from eDRAM's lower latency but Intel keeps shooting itself in the foot with regards to taking advantage of its memory products (hello Optane!).

 

[JoeRambo]

I was comparing latency of eDRAM to that of DDR5. ADL with DDR5-4800 could have benefited from eDRAM's lower latency...

I believe the problem with eDRAM deployment would be cost/benefit being too low.

Intel already has hilariously slow LLC cache, that would not be out of place in mobile phone. And adding eDRAM would make L3 even slower -> currently cores have L3 cache slices, placement is decided by address hash. They would need somewhere to store tags for what is in eDRAM, so a chunk of L3 would be allocated and even more checks would happen in parallel, slowing each L2 miss down and burning energy.
It is less tradeoff than in Broadwell era, when 2 out of 8MB of L3 cache went for eDRAM tags. But the problem is that with 30-36MB of L3, to make impact to hitrates they would need minimum 128MB of eDRAM. Then there is a question of eDRAM controller, either it is another stop on ring or shares IMC, also does not come free in latency.

There is a way to use eDRAM as system level cache, like Apple does for its SRAM pools that help with iGPU etc, but unlike SRAM (even its slower, power saving friendly one incarnation), eDRAM is slow. So you miss LLC ( 20ns affair in Intel's design) and then what? check eDRAM for 30ns miss and then take full DRAM latency? burn SRAM area for tags that can just be used as LLC SRAM ?

So that is why eDRAM is dead in Intel's world. Too bad for them, AMD is starting to beat them with a log sized stick, with X3D written on it and it can get only worse till they get similarly sized SRAM pool on their server chips.

 

[DrMrLordX]

That is not how it Ryzen Master works.

We're getting a little off-topic here, so let me show Ryzen Master on my system:



Here's Ryzen Mater and HWiNFO64 reading a CBR23 run while my 3900X runs at default. I don't know how Mark has his set up, but this is what mine looks like. The actual power draw, as you can see, is ~142W which is reflected in the PPT above as well as the PPT field in HWiNFO64, wheras CPU power is only ~114W (Ryzen Master and HWiNFO64 have slightly different readings here).

 

[DrMrLordX]

I believe the problem with eDRAM deployment would be cost/benefit being too low.

Plus if Intel ever tightened up their memory controllers again, all of eDRAM's advantages would evaporate except on devices that are certain to have slow RAM.

 

[JoeRambo]

Here's Ryzen Mater and HWiNFO64 reading a CBR23 run while my 3900X runs at default. I don't know how Mark has his set up, but this is what mine looks like. The actual power draw, as you can see, is ~142W which is reflected in the PPT above as well as the PPT field in HWiNFO64, wheras CPU power is only ~114W (Ryzen Master and HWiNFO64 have slightly different readings here).

I am well aware of this, You should be really replying to mr. "I skipped elementary math". PPT => what CPU is actually drawing. Here's his claim, obviously Your RM is not displaying 135% either:

PPT is at 142W and is 135% of the TDP.

When 103% is displayed it means that the CPU is at 103% of its rated TDP, if it reach 142W then 135% is displayed.

 

[DrMrLordX]

Your RM is not displaying 135% either

My Ryzen Master is displaying data differently than his. He's listing percentages of TDP, while mine lists percentage of PPT. Unless he's just misreporting from Ryzen Master. Which he might be.

In any case, the whole point of pasting that was to show what the application reads, at least on my end, to clear things up so we can move on to some other topic that is actually related to Zen4.

 

[nicalandia]

My Ryzen Master is displaying data differently than his. He's listing percentages of TDP, while mine lists percentage of PPT. Unless he's just misreporting from Ryzen Master. Which he might be.

In any case, the whole point of pasting that was to show what the application reads, at least on my end, to clear things up so we can move on to some other topic that is actually related to Zen4.

Please Let's get back at this Topic.

So Max Boost for a Certain SKU is going to be 5.85 Ghz(not likely the Top SKU but perhaps second)

Gold Plated CCDs for better thermals and conductivity

 

[PJVol]

AMD TDP has less to do do with power and more to do with recommended heatsink properties, Intel TDP is literally a package power limit.

Honestly it's not totally clear for me, why these two metrics together exist, unless PPT reflects power dissipation related to both thermal and electrical design currents (for the CCDs and IOD), while TDP rely more on thermal resistance for the stock cooler.
How far from the truth do you think this is?

 

[DrMrLordX]

So Max Boost for a Certain SKU is going to be 5.85 Ghz(not likely the Top SKU but perhaps second)

Again, we don't know that, since Fmax for the 5950X is higher than it's top boost rating; that being said, sometimes any Zen3 may boost over its listed max boost so that may just be an instance of the chip running up against its fused Fmax.

Gold Plated CCDs for better thermals and conductivity

It's mostly just there to improve soldering.

Honestly it's not totally clear for me, why these two metrics together exist, unless PPT reflects power dissipation related to both thermal and electrical design currents (for the CCDs and IOD), while TDP rely more on thermal resistance for the stock cooler.
How far from the truth do you think this is?

In the case of an AM4 CPU with, let's say a TDP of 105W and an HSF that can handle up to ~180W, PPT reflects how high power draw can get while it boosts so long as it stays within thermal constraints (which will be forever since the HSF should handle the heat load assuming its installed correctly). If you have the same CPU with the same installation quality but using an HSF that can handle ~105W, then PPT will only come into play until the HSF gets heat soaked, forcing power draw back closer to the TDP to stay within thermal constraints. Under circumstances where the CPU throttles back power draw to TDP, AMD only guarantees the chip to run at its base clocks. Or close to it.

Example: my 3900x shown above maintained 4175 MHz @ 142W power draw, but if thermally-limited by the cooling solution, it would probably drop to 3800 MHz @ 105W.

AM5 will likely behave the same way.

 

[coercitiv]

Honestly it's not totally clear for me, why these two metrics together exist, unless PPT reflects power dissipation related to both thermal and electrical design currents (for the CCDs and IOD), while TDP rely more on thermal resistance for the stock cooler.
How far from the truth do you think this is?

For AMD the TDP rating is defined using a combination of cooler thermal properties, target temp for the CPU and maximum ambient temp. It's a bit backwards really, because it's utility is to depart from a TDP target like 65W and then punch in requirements for CPU temp and ambient temp, and this will result in a minimum cooler performance (thermal resistance) required for the CPU to hit base clocks under the most unfavorable environment (the ambient temp specified earlier).

However, the TDP equation is great at figuring out the power/cooling balance for prolonged periods of heavy load, but fails to take into account the thermal reserves the system may have due to heatsink heat capacity or lower ambient temps (case, room etc). This creates the opportunity for higher burst performance for short, medium and maybe even longer periods of time. This is where PPT comes into play, defining a higher power ceiling that the power management algorithm can take into account to boost performance for a seemingly limited period of time.

The trick with PPT is what value one aims for: the higher you set PPT relative to TDP, the lower the time delta until heatsink gets saturated and the higher the VRM requirements become especially on budget boards. Efficiency also goes down, but we'll ignore that. So the general rule of thumb is to increase PPT by a high enough margin that can be sustained for tens of seconds, maybe a minute or two (obviously real-world conditions vary greatly). Turns out using a relative ratio of 1.2 - 1.4x TDP is a good compromise between performance and burst length, so that's why both Intel and then AMD opted for this 1.25-1.35x range. Later on Intel went full clown mode with their PL2 power limits, but ironically enough it's only a marketing decision, if you look in Intel's engineering driven documentation for any modern consumer CPU you'll see the same range of ~1.3x TDP with 30-60 seconds of uptime. AMD seems to follow suit with increasing power limits, but at least they're consistent and will increase TDP, not PPT ratio. Not great, not horrible.

So TDP and PPT are complementary metrics aimed at extracting a higher amount of performance for a given cooler class. You can't (optimally) have one without another, since they define different limits for the system and removing any of them alters performance or cost requirements.

 

[PJVol]

PPT reflects how high power draw can get while it boosts so long as it stays within thermal constraints

This is actually what TDP should define, being thermal design constraint together with total thermal resistance which in turn mostly depends on θSA of the heat sink.

 

[DrMrLordX]

This is actually what TDP should define, being thermal design constraint together with total thermal resistance which in turn mostly depends on θSA of the heat sink.

It doesn't though. TDP approximately the power draw when the CPU is held to base clocks.

 

[PJVol]

It doesn't though. TDP approximately the power draw when the CPU is held to base clocks.

I'm afraid you either got this wrong or being inexact. Perhaps you did mean under the heaviest possible workload with the CPB disabled? That very well may be the case, but still has nothing to do with the CPU operating at stock settings, where additional heat generated with CPB-ON was taken into account in thermal design.
I can't recall how my 3600X behaved at stock (got rid of it), but 5600X is almost always PPT limited (76W) in heavy loads, be it water or air cooled.

The trick with PPT is what value one aims for: the higher you set PPT relative to TDP, the lower the time delta until heatsink gets saturated and the higher the VRM requirements become especially on budget boards.

Yeah, I forgot about that, and it's certainly worth mentioning.
As for the rest of your post, I don't see it as much inconsistent with my view of the PPT/TDP relationship.

 

[kognak]

That s not 146W.

TDP is 105W and PPT is 142W.

So the CPU can get up to 135% of the TDP, that is 142W.

In the case of Mark his CPU use 103% out of 135% of the PPT, so his 110W is right.

Btw, in CB the 5950X use 125W@4GHz.

110W is just power consumption of CCDs, not whole CPU. "103% of 142W" is 146W. It's not 110W. And TDP doesn't really even exists, it's meaningless number chosen by AMD in relation to PPT. For example 5600/X PPT is just 17% higher than TDP. Threadripper and Epyc TDPs are same as PPT. Odd thing is it's going over 100%, normally it shouldn't. Probably a little bit deviation in reporting. My 5800X's CCD is using 91W and total consumption is 120W(100% of 120W). Again not perfectly accurate as HWinfo is reporting 123W.

 

[Abwx]

110W is just power consumption of CCDs, not whole CPU. "103% of 142W" is 146W. It's not 110W. And TDP doesn't really even exists, it's meaningless number chosen by AMD in relation to PPT. For example 5600/X PPT is just 17% higher than TDP. Threadripper and Epyc TDPs are same as PPT. Odd thing is it's going over 100%, normally it shouldn't. Probably a little bit deviation in reporting. My 5800X's CCD is using 91W and total consumption is 120W(100% of 120W). Again not perfectly accurate as HWinfo is reporting 123W.
View attachment 62336

The 5800X consume as much as the 5950X as reported by Computerbase, and even a little more since it idle a little lower, so that s just more argument about my point.

FTR idle comsumptions for full system is 52W for the 5800X and 56W for the 5950X, at full Cinebench loading powers are 198W and 199W respectively, the delta do not point to 142W even if we account for the CPU 15-18W uncore power.

It is below 199W full system even with Prime 95.

AMD Ryzen 5950X, 5900X, 5800X & 5600X im Test: Leistungsaufnahme und Temperatur

AMD Ryzen 5000 im Test: Leistungsaufnahme und Temperatur / Leistungsaufnahme von Leerlauf bis Volllast

www.computerbase.de

 

[kognak]

The 5800X consume as much as the 5950X as reported by Computerbase, and even a little more since it idle a little lower, so that s just more argument about my point.

FTR idle comsumptions for full system is 52W for the 5800X and 56W for the 5950X, at full Cinebench loading powers are 198W and 199W respectively, the delta do not point to 142W even if we account for the CPU 15-18W uncore power.

It is below 199W full system even with Prime 95.

AMD Ryzen 5950X, 5900X, 5800X & 5600X im Test: Leistungsaufnahme und Temperatur

AMD Ryzen 5000 im Test: Leistungsaufnahme und Temperatur / Leistungsaufnahme von Leerlauf bis Volllast

www.computerbase.de

These numbers from the wall align very well with 142W power limit. 5800X at stock has 142W PPT, cores get around 120W(idle package power is higher than SoC power). VRM+PSU efficiency is about 80%. 120W/0.8 = 150W. 150W + 52W = 202W.

 

[Schmide]

Computex: Beyond the Coverage

What they didn't tell you.

www.angstronomics.com

Skygod strikes again!

Seriously though, read this article.

Very well written. Good start for a site.

I was plopping around the cesspools of chip trolls* and people are complaining about the 4x pcie4 downlink to the two daisied chipsets.

I think this design really has some merit. It pushes much of the noisy switched IO to dedicated chips while reserving lanes directly off the CPU. If you actually look at the diagrams, off the CPU there are 20x pcie5 lanes available to the graphics and ssd (16x or 8x/8x + 4x), then a 4x pcie4 for USB4 switch, followed by bunch of DP/USB32/GPIO/HDAudio dedicated ports, with the final 4x pcie4 for all the diasied chipsets.

Looks really rich in IO to me.

*After AdoredTV quoted the silicongang I wandered into their rabbit holes.

 

[Abwx]

These numbers from the wall align very well with 142W power limit. 5800X at stock has 142W PPT, cores get around 120W(idle package power is higher than SoC power). VRM+PSU efficiency is about 80%. 120W/0.8 = 150W. 150W + 52W = 202W.

For the 5950X the delta is 143W and efficency of the supply chain is more like 0.775, so that makes 111W for the CPU to wich 15W should be added as uncore power, that makes 126W for the package power.

In Prime 95 the delta is 133W, so CPU power is even lower than with Cinebench and at someting like 118W.

 

[Timmah!]

Very well written. Good start for a site.

I was plopping around the cesspools of chip trolls* and people are complaining about the 4x pcie4 downlink to the two daisied chipsets.

I think this design really has some merit. It pushes much of the noisy switched IO to dedicated chips while reserving lanes directly off the CPU. If you actually look at the diagrams, off the CPU there are 20x pcie5 lanes available to the graphics and ssd (16x or 8x/8x + 4x), then a 4x pcie4 for USB4 switch, followed by bunch of DP/USB32/GPIO/HDAudio dedicated ports, with the final 4x pcie4 for all the diasied chipsets.

Looks really rich in IO to me.

*After AdoredTV quoted the silicongang I wandered into their rabbit holes.

Do you think PCI-E 5.0 x8 would be good enough for rtx4090? Does it still count that 8x of the latest generation is the same as 16x of the previous one?

 

[Kepler_L2]

Do you think PCI-E 5.0 x8 would be good enough for rtx4090? Does it still count that 8x of the latest generation is the same as 16x of the previous one?

According to kopite7kimi RTX 4000 is still PCIe Gen4.