Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Saylick]

I can't quite remember whether it's cache that benefits most from a node shrink or whether it benefits the least. Or am I confusing all this for the memory controllers in the IOD. Possibly the less bandwidth sensitive Chiplet MCD structure of RDNA3 that's still on 6nm that's throwing me off.

Per TSMC:

 

[nicalandia]

Okay, took me a while to find the correct diagram.

Based on this

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

This is the exact position of each 8 core CCD Of Genoa,



Bergamo will use the same substrate package and size, so the position of the CCD its important to fit 4 CCDs per quadrant.

Based on the Ryzen 7000 Raphael two CCD position one could Fit 4 CCDs per quadrant even if their size remains the same, so AMD has options here.

Top Left Quadrant with 4 CCDs with 8 core each, full cache.

 

[eek2121]

Has anyone seen if they can activate the other cores on the 7900X? Since Chips&Cheese was able to deactivate 3 cores per CCD to fake a 10 Core 7800X

I hope AMD pushes out a 10 core chip just to troll Chips&Cheese. I would personally buy one to support trolling them. What they did honestly wasn't right. Yes you can fake the CPUID, many of us with development or IT already knew that. By pulling a stunt like that, they are welcoming even more fakes. Previously fakes were actually pretty rare and easy to spot. Very few users go to the effort of creating a realistic fake. They changed all that with their nonsense.

Okay, took me a while to find the correct diagram.

Based on this

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

This is the exact position of each 8 core CCD Of Genoa,


Bergamo will use the same substrate package and size, so the position of the CCD its important to fit 4 CCDs per quadrant.

Based on the Ryzen 7000 Raphael two CCD position one could Fit 4 CCDs per quadrant even if their size remains the same, so AMD has options here.

Top Left Quadrant with 4 CCDs with 8 core each, full cache.

Say it with me: AMD isn't releasing Bergamo on desktop or mobile.

 

[DisEnchantment]

Okay, took me a while to find the correct diagram.

Based on this

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

This is the exact position of each 8 core CCD Of Genoa,
View attachment 70196


Bergamo will use the same substrate package and size, so the position of the CCD its important to fit 4 CCDs per quadrant.

Based on the Ryzen 7000 Raphael two CCD position one could Fit 4 CCDs per quadrant even if their size remains the same, so AMD has options here.

Top Left Quadrant with 4 CCDs with 8 core each, full cache.
View attachment 70197

To me it seems they will only need to use 8x CCDs with dual CCX each for Bergamo.

• Density optimized Zen 4c library > 15% MTr/mm2 vs vanilla Zen 4 (see Zen 3 Mobile vs Zen 3 CCDs as a comparison, at the end of the post)
• N4 is also ~6% Higher MTr than vanilla N5 family. Not sure how much for AMD's flavor of N5 but lets say some mid single digit percent more MTr/mm2.
• L3 cut in half
• Dual GMI links already present in the Zen 4 CCDs.
• IOD and substrate already already designed to handle dual GMI per CCD, i.e. handle up to 16 CCXs.
• Probably just need some RDL on the Zen 4c CCDs to make contacts with the same Genoa IOD.

The new processor is 180 mm2 in size, compared to 156 mm2 of last generation, but still fits into the same socket. It contains 10.7 billion transistors, which is up from 9.8 billion.

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On N7 Ryzen 5000 Mobile is ~60 MTr/mm2 compared to ~51 MTr/mm2 for Ryzen Zen 3 CCDs.

 

[nicalandia]

Say it with me: AMD isn't releasing Bergamo on desktop or mobile.

I don't believe I implied that with the diagram.

 

[biostud]

Still waiting for Zen 4X3D chips and next gen GPUs that don't use melting +12VHPWR connectors to upgrade

Same

 

[biostud]

Weird...

https://twitter.com/x/status/1587732411525349377

 

[Rekluse]

Cache is benefiting less and less from node shrinks, however, apparently, choosing different design libraries can notably influence it's density. AMD mentioned that with respect to the 3D Cache on the 5800X3d that they had used a cache optimized design rule set for the cache die. I suspect that using a higher density library for Bergamo won't be focused on cache density.

That clears things up. It begs the question though, whether vertically bonded stacking is viable for more than just L3. Curious whether they could get away with creating a full logic chip and a cache chip aligning the via's directly on the logic beneath.

Per TSMC:
View attachment 70191
View attachment 70190

So Logic Density benefits the most and Analog the least. SRAM barely any better than Analog.

 

[nicalandia]

AVX-512 Performance

7700X vs 11900K, 8C/16T performance.

"While initially leary of AMD Zen 4's "double pumped" approach for supporting AVX-512 using a 256-bit data path, it's proven to be very efficient for performance and yield great results without negative clock impairments or wreaking havoc on the power consumption"

AMD Ryzen 7 7700X vs. Core i9 11900K AVX-512 Performance Analysis Review - Phoronix

www.phoronix.com

 

[igor_kavinski]

View attachment 70251

Nice 44% increase on their first attempt. They have some really bright engineers working there. I'm hopeful that AMD will also show Intel how to do E-cores right.

 

[moinmoin]

I'm hopeful that AMD will also show Intel how to do E-cores right.

I hope so as well. By never using that concept at all.

 

[nicalandia]

I hope so as well. By never using that concept at all.

Yeah, more like CCD gating or fine grained tuning how each CCD works. Most games will never exceed 8 Cores, so use a single CCD for gaming, the rest can be gated to be used by the OS on the background at a much lower clocks.

 

[Kaluan]

AVX-512 Performance

7700X vs 11900K, 8C/16T performance.

"While initially leary of AMD Zen 4's "double pumped" approach for supporting AVX-512 using a 256-bit data path, it's proven to be very efficient for performance and yield great results without negative clock impairments or wreaking havoc on the power consumption"

View attachment 70248

View attachment 70250

View attachment 70251

AMD Ryzen 7 7700X vs. Core i9 11900K AVX-512 Performance Analysis Review - Phoronix

www.phoronix.com

Dang, the overall thing lines up almost sublimely. Edging out Intel w/ AVX512 in aggregate performance w/o AVX512 and using like 3W less w/ AVX512 were as Intel needing 30W+ more (on top of it's already terrible ~205W w/o).

Can't wait for my Raphael/Raphael-X Linux machine in Q1 next year.

 

[Rekluse]

I hope so as well. By never using that concept at all.

Frankly I used to agree with this sentiment. But thinking about it, E-cores are really just Intel's desperate attempt to match AMD's multithreading performance while retaining some marginally rational power consumption figures. Which really is the wrong way of going about things

I would be far more enthusiastic with the AM5 platform remaining Full performance and Zen4c free, maxing out at 16 cores.
Then having a separate, much more reasonably priced Threadripper TR6 with a hybrid Zen4 Chiplet and a Zen4c Chiplet maxing out at 24 cores. Or all Zen4c option maxing out at 32 cores.

My use case would be running Zen4 cores for a VM and Zen4c for Docker Containers. But that's just me.

 

[LightningZ71]

Personally, I could find good use for a Zen 4 processor setup with two CCDs, one with a full performance N5 8 core CCD (with a nice 3D cache stack if they could make the memory manager understand the different L3 sizes) and a second CCD that has two CCX with 8 cores each and 16MB L3 using a high density/high efficiency library. I could have the first CCD be allocated to my main OS and use the other CCD for VMs for various homelab functions that I could shut down if I needed maximum thread throughput on a specific task. While I wouldn't find a 16 core processor overly limiting, having 24 cores to play with would be better. I admit that my use case would be a bit unusual, and I currently work around it by just using multiple headless PCs instead.

 

[Kaluan]

Speaking of high density, how does the Zen4 TSMC 'N5' 32MB L3 SRAM compare in die space/size with Zen3's TSMC 'N7' 32MB L3 SRAM? Or the 1MB vs 512KB L2s?

 

[DisEnchantment]

My use case would be running Zen4 cores for a VM and Zen4c for Docker Containers. But that's just me.

For 32+ Cores, under full load Zen 4c = Zen 4 in frequency (with reasonable TDP), and same uarch.
So actually if you don't care so much about half L3 ( supposedly ), Zen 4c would be better from efficiency standpoint.

TSMC's Shmoo plot put N5 HD lib highest optimal frequency at 4.1 - 4.2 GHz. Could be better for N4.

Speaking of high density, how does the Zen4 TSMC 'N5' 32MB L3 SRAM compare in die space/size with Zen3's TSMC 'N7' 32MB L3 SRAM? Or the 1MB vs 512KB L2s?

~30% smaller, in line with TSMC's numbers. Removing GMI and SMU and Debug and TSV, Zen 4 Core is quite small.

 

[Kaluan]

For 32+ Cores, under full load Zen 4c = Zen 4 in frequency (with reasonable TDP), and same uarch.
So actually if you don't care so much about half L3 ( supposedly ), Zen 4c would be better from efficiency standpoint.

TSMC's Shmoo plot put N5 HD lib highest optimal frequency at 4.1 - 4.2 GHz. Could be better for N4.


~30% smaller, in line with TSMC's numbers. Removing GMI and SMU and Debug and TSV, Zen 4 Core is quite small.
View attachment 70279

Thank you! 😊


YT "premiere" for the 3rd "together we advance_" (datacenters) is up on AMD's channel, 7+ days in advance.

Besides Genoa, Bergamo, Siena and maybe Genoa-X, what are the odds we get some teaser details on Turin/Zen5?

 

[bsp2020]

For 32+ Cores, under full load Zen 4c = Zen 4 in frequency (with reasonable TDP), and same uarch.
So actually if you don't care so much about half L3 ( supposedly ), Zen 4c would be better from efficiency standpoint.

What I'm wondering is whether AMD would ever make Zen4c/Zen5c + V-cache. I'd think that it would give a much higher density and efficiency compared to normal Zen4/Zen5, especially if they can use cache die using n-1 process node.

 

[Saylick]

Besides Genoa, Bergamo, Siena and maybe Genoa-X, what are the odds we get some teaser details on Turin/Zen5?

Likely 0% lol

 

[Kaluan]

Likely 0% lol

Yeah I'm not holding out for much. We did get confirmation on Zen5+V-Cache, Zen5c and "4nm" and "3nm" being used for Zen5 at the "..._PCs"/Ryzen 7000 one tho. So eh.

We could get some more details on Ryzen 7000X3D tho, through possible detailing of Genoa-X. Then again, I'm one who thinks we may get some more info on Zen4 V-Cache tomorrow, at the RDNA3/gaming event... 😅

 

[A///]

I hope AMD pushes out a 10 core chip just to troll Chips&Cheese. I would personally buy one to support trolling them. What they did honestly wasn't right. Yes you can fake the CPUID, many of us with development or IT already knew that. By pulling a stunt like that, they are welcoming even more fakes. Previously fakes were actually pretty rare and easy to spot. Very few users go to the effort of creating a realistic fake. They changed all that with their nonsense.

that was the online paper that did the fake skus right? they lost all credibility with that stupid stunt. when you do stunts worse than wccftech you deserve to be ignored forever.

 

[A///]

Thank you! 😊


YT "premiere" for the 3rd "together we advance_" (datacenters) is up on AMD's channel, 7+ days in advance.

Besides Genoa, Bergamo, Siena and maybe Genoa-X, what are the odds we get some teaser details on Turin/Zen5?

young kaluan the padawan has learned from sensei. bows

With great power comes great responsibility. journey safe, friend.

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[itsmydamnation]

that was the online paper that did the fake skus right? they lost all credibility with that stupid stunt. when you do stunts worse than wccftech you deserve to be ignored forever.

Ok you can ignore the only people doing Mirco arch investigations these days, I'll just shake my head at you and wait for their next high quality investigation .

 

[yuri69]

Besides Genoa, Bergamo, Siena and maybe Genoa-X, what are the odds we get some teaser details on Turin/Zen5?

When was the last time AMD teased with a major product scheduled for 1-2 years in advance? Just a reminder, Zen 5 is *not* a 2023 product - it is 2024. 2023 is the same season as 2021/2022 was - riding a V-Cache wave.