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Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

Senior member
Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

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What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! 🙂
 
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I'm a bit confused, are they signaling that synchronous speeds with FLCK max out at 5200-5600 (2600-2800)?
On ES hardware, yes.

Hopefully this gets better on release hardware and we can run ~5800-6000 MT/s synced with even lower latency 😇
Same way AMD said 4000MT/s (2000 flck) was the sweet spot for Zen3 and we ending up @ 3800MT/s (1900flck) instead for pretty much all dual CCD cpus.
(many 5600x's and 5800x's can do ~2000 flck without WHEA reduction to performance)
 
Thanks, I guess close to 6000 is quite decent since it seemingly requires pushing the existing tech further given how the system/chipset is similar (except for DDR5). I would have hoped for the 2x scaling that DDR5 provides ideally though (to guaranteed ~7500 ish).
 
Well, it is Geekbench blah. :mask:

Correct me if I am wrong, but isn't the test they did limited to supporting 256 threads ? So the 28% was using 256 of the 384 available threads and still 28% faster ?
 
Correct me if I am wrong, but isn't the test they did limited to supporting 256 threads ? So the 28% was using 256 of the 384 available threads and still 28% faster ?

Geekbench doesnt scale like Cinebench, with that much cores and threads it s surely well below 50% scaling.
 
Looks like single core was 17% faster and at essentially the same frequency as the Zen3 core, unless I'm missing something.
Yes, thats what I saw. But I didn't get that if its 17% faster,, and 50% more cores, then why only 28% more total ???? Its a crap test IMO. I want to see some real benchmark that uses 384 threads. What I wouldn't give to have a pair of those for my DC work !
 
So, all of the parts talked about so far at 9000 series? I wonder if the cutdown SP6 socket parts going to be 7000 series with 8 chiplets and 8 channel memory max? Has anything been said about that?
 
So, all of the parts talked about so far at 9000 series? I wonder if the cutdown SP6 socket parts going to be 7000 series with 8 chiplets and 8 channel memory max? Has anything been said about that?
AMD said 64 Zen4 cores on Siena platform (SP6), so this is going to be 8 chiplets + X memory channels. It's most likely 8 channels (4 numa nodes * 2 channels per node), but maybe small chance of being 6 channel.
 
Well, it is Geekbench blah. :mask:


“What we do know is that only one AMD architecture now features 96-cores and that’s EPYC Genoa based on Zen4.”

Well, technically, it seems like there could be a 96 core Bergamo based chip, 16 CCX (8 CCD) x 6 cores per CCX, rather than the full 8 cores. A 64 core with only 4 cores active per CCX seems plausible also. That could be done with just 4 CCD with the full 8 cores per CCX though. I guess they could make some variants with higher cache per core with the low core count versions (64 or less is kind of low core count, I guess).
 
So, all of the parts talked about so far at 9000 series? I wonder if the cutdown SP6 socket parts going to be 7000 series with 8 chiplets and 8 channel memory max? Has anything been said about that?

The current generation / socket is the 7000 generation with last digit specifying Zen1, 2 and 3.

9000 generation will be socket SP5
8000 will then likely be the Sienna socket SP6 (my guess)
 
AMD said 64 Zen4 cores on Siena platform (SP6), so this is going to be 8 chiplets + X memory channels. It's most likely 8 channels (4 numa nodes * 2 channels per node), but maybe small chance of being 6 channel.
I would expect only 4, 8, or 12 channels with 1, 2, or 3 channels per quadrant (4 numa per socket). I don’t think they would move to a different organization in the IO die, so 6 channel seems very unlikely. Early on, I had thought that they might do such a thing by making a modular IO die such that 2, 4, or 6 chips could be used for just the IO die, but it seems to be a big monolithic die still.
 
The current generation / socket is the 7000 generation with last digit specifying Zen1, 2 and 3.

9000 generation will be socket SP5
8000 will then likely be the Sienna socket SP6 (my guess)

Doesn’t seem like a very good naming scheme, but the usually aren’t.
 
Well, it is Geekbench blah. :mask:

As usual, WCCF with their rubbish comparisons using Geekbench and Videocardz regurgitating it. Didn't bother checking the Geekbench version (which is different), kernel version (which is also different) and on top of that they are comparing the overall scores instead of integer and fp scores individually. There's a lot of variance in performance between kernel version 4.18 and version 5.11, and probably half of the improvement can be explained by that difference alone.

Here's my actual analysis of the Geekbench result, using the same Geekbench version and kernel version:


The takeaway is that perf/clock in Geekbench is lower than what AMD is claiming with 8-10% IPC.
 
As usual, WCCF with their rubbish comparisons using Geekbench and Videocardz regurgitating it. Didn't bother checking the Geekbench version (which is different), kernel version (which is also different) and on top of that they are comparing the overall scores instead of integer and fp scores individually. There's a lot of variance in performance between kernel version 4.18 and version 5.11, and probably half of the improvement can be explained by that difference alone.

Here's my actual analysis of the Geekbench result, using the same Geekbench version and kernel version:


The takeaway is that perf/clock in Geekbench is lower than what AMD is claiming with 8-10% IPC.

Interesting
 
So, all of the parts talked about so far at 9000 series? I wonder if the cutdown SP6 socket parts going to be 7000 series with 8 chiplets and 8 channel memory max? Has anything been said about that?

I remember 6 channels. Nothing official though...
 
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