Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

Page 162 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Vattila

Senior member
Oct 22, 2004
799
1,351
136
Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

Untitled2.png


What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts! :)
 
Last edited:
  • Like
Reactions: richardllewis_01

Henry swagger

Senior member
Feb 9, 2022
356
235
86
Chu
Some back of the napkin math. If the rumor about 18% IPC and 7% all core boost increase and 8.7% single core boost.
Cinebench r23
Single Core would be around 2140 (single core boost of about 5.35Ghz +18% IPC)
Multi Core would be around 36300 (mulit core boost of about 4.5Ghz +18% IPC)
This assumes pretty much perfect scaling with IPC and frequency (I know that is almost never a thing)

I have no idea if the rumor from chiphell is even close, but if it is Zen 4 is looking pretty darned good.
I think the CPU market over the next few years for consumers is going to be great -- the performance available for desktop users is going to be ridiculous.
Chiphell is pretty accurate..
 

deasd

Senior member
Dec 31, 2013
513
724
136
If that 18% IPC increase is relative to zen3, that would be underwhelming, but if this is relative to zen3D, then that's huge.
underwhelming? what did you expect from Zen4? 25%? 30%? that's less possible if you compare Zen+ to Zen2 which was also a process node + architecture enhanced, and result in 15% IPC difference. Also Zen3D won't have that uplift since architecture has no change.

Chu
Chiphell is pretty accurate..
Chiphell has so many bad track record. so that's why I said Rumor. And I don't think there would be any AMD CPU release in April...
 
  • Like
Reactions: Tlh97 and Bigos

soresu

Platinum Member
Dec 19, 2014
2,617
1,812
136
Also Zen3D won't have that uplift since architecture has no change.
It does for some apps/tasks, we still have only a limited sampling of the improvement it will bring, and even then only from an 8 core SKU.

There's also a possibility that the value could be the improvement of the Zen4 V cache SKUs relative to Zen3D.
 
  • Like
Reactions: Kaluan

MadRat

Lifer
Oct 14, 1999
11,909
229
106
The opposite seems more likely. The Epyc IO die may be very pad limited without some advanced packaging technology. It is not that large and it somehow has 12 channel DDR5, 128 pci-express 5, and 12 cpu die connections. That is a ridiculous number of pads required.

The consumer IO die will likely only have 2 channel memory and 32 high speed serdes for pci-express, SATA, etc. The gpu that is included has been rumored to be very small. It is just there to provide roughly the same features across the whole line. This makes it look like they may make the consumer IO die at GF and the Epyc IO die at TSMC.
That would make sense for a laptop or tablet as an OEM could aim for greatly lower specs. But haven't all Zen generations allowed paring down components with the SOC engineering? It would make sense that OEMs could target niches inline with their price targets.
 

jamescox

Senior member
Nov 11, 2009
637
1,103
136
I doubt they would have put the IGP in there if the IO die was using a GloFo node. It has to be N6.
There have been rumors of a low end GF APU, so making a small gpu on GF doesn’t seem like it is an issue. For a very small gpu, it will be quite a bit of area spent on display drivers (IO) and probably a bit on hardware video encode/decode.
 
  • Like
Reactions: Tlh97 and Joe NYC

Asterox

Golden Member
May 15, 2012
1,026
1,775
136
Cache size changes do impact IPC, that's why e.g. the Ryzen APUs so far are worse off. (So with Intel segmenting also by cache size even when using the same die the IPC would technically need to be measured for every SKU with a different cache size.)

In gaming yes or usually, but in other test or aplications the diference can be very small.As we can see, R5 4650G/8MB L3 can be faster vs R5 3600/32mb L3.

L3 cache difference or size is huge no doubt.

Collision of two Zen 2 processors, but 4000 Renoir is monolithic CPU design+much beeter memory controler.


R5 5600G/16mb L3 vs R5 5600X/32mb L3, there is a hm much more pleasant L3 cache size difference. :grinning:
 
Last edited:

jamescox

Senior member
Nov 11, 2009
637
1,103
136
I'm not sure what the argument here is. All of that IO is precisely what doesn't benefit from a node shrink to the same degree as logic or even SRAM does. Why use an advanced node when you can't shrink below a certain size for the very reason you outline?



It doesn't matter if the GPU itself is small in the sense that it only has 2 compute units. Look at a die annotation for any of AMD's APUs and see how much additional logic is included so that the GPU can actually connect to a display.

YtxGU48DGLgI2sCX.jpg

Source: https://www.techpowerup.com/264801/amd-renoir-die-shot-pictured

Even though it's not a powerful GPU it still needs to include a lot of other circuitry that isn't a shader just to function as a GPU. I wouldn't be surprised if most of the transistors dedicated to the GPU aren't going to the shaders. Some of that (e.g. ROPs) can scale downward with the reduced number of CUs, but other parts can't.



Although it seems that way on the face of things, you actually have it backwards. AMD faces fiercer competition in the desktop space than they face in server right now. The advantages that they have in terms of the number of cores and the efficiency of those cores will mean that even if the IO die isn't as efficient as it could be they'll still come out on top. Meanwhile on desktop where there will be more fierce competition, any advantage that AMD can get will benefit them.

I mentioned that the desktop IO die for Zen 2/3 is about 125 mm^2. Meanwhile the IO die used on Epyc CPUs is over 400 mm^2 and that's for the current dies which only have 8 memory channels and connect to at most 8 chiplets. AMD can get roughly 4x as many desktop IO dies from a wafer as they can server IO dies. The only real justification for using it for servers is that the server chips can better absorb the extra cost of using TSMC for an IO die since they're a higher margin part.

What advantage would a TSMC IO die bring to desktop parts? You can’t have it both ways. If the power consumption of an GF IO die is a problem on the desktop (not very sensitive to power consumption) then it is a much bigger problem for Epyc where power consumption is a much bigger concern. People don’t really care about power consumption of desktop parts very much, especially at the mid to high end. The IGP is mostly irrelevant for 8 to 16 core desktop parts also; it is expected to be paired with a dedicated GPU.

If I am not mistaken, the IO die for Genoa has been rumored to be smaller than than the Rome/Milan IO die which is something like 435 mm2 compared to the gigabyte leak which places the Genoa IO die at ~397 even though it contains significantly more units (8 DDR4 -> 12 DDR5, 8 -> 12 GMI for cpu die). That is with a speed increase to pci-e 5 levels or above for all GMI and pci-e serdes, which likely takes more hardware in the PHY. If that 397 is on 6 nm, then how large would it have been on GF? 500 mm2? I don’t know how GF latest compares to TSMC 6 nm; is it even possible that this is on GF?

It is only the physical interfaces that do not shrink since they need to be a certain size transistors to provide sufficient power to drive off package IO. A lot of stuff on the IO die will shrink. One of the large components is the UMC (unified memory controller) which is somewhat independent of the memory type; Genoa has 12 of those. They will all be logic and buffers since it is separate from the memory PHY. The infinity fabric part will also shrink. The Epyc IO die has a huge amount of infinity fabric connections that will just be logic, buffers, and interconnect. It is only the PHY portion for the off chip interface that will not shrink much. If Bergamo uses stacked silicon bridges, then all of the GMI PHY for cpu die go away; one of the reasons that I think it could be a single reticle sized device.

I think the main argument for a TSMC made Genoa IO die is the packaging tech required. They made it smaller but increased the IO pads significantly. It will likely use some form of advanced packaging technology to route all of those signals out of the die. The routing is ridiculously complicated even for the Rome/Milan IO die. The Genoa IO die is still a big die, but it has a ridiculous amount of IO. A lot of the advanced packaging technologies require that all of the die be made at TSMC. The desktop IO die likely doesn’t need any advanced packaging and isn’t very sensitive to power consumption. This seems like a good candidate for GF production. They technically could take advantage of the chipset production by making it actually the same as the IO die. Current chipsets are, at a minimum, the same floor plan as the IO die; they contain the same thing, the memory controller just goes unused in the chipset.

I expect that the MCM desktop parts will be a bit of a niche / enthusiast part anyway. The extreme low end may be a GF made APU. The low to mid range (4 to 8 cores) may be a TSMC made APU. The mid to high end (high end 8 core to 16+ core) could then be the MCM version. These would probably have higher clocks and significantly more cache than the APU. I don’t know whether they will bother making desktop IO die at TSMC, but it seems like there is a lot of evidence pointing towards Epyc IO die going TSMC.
 

gruffi

Member
Nov 28, 2014
35
117
106
underwhelming? what did you expect from Zen4? 25%? 30%? that's less possible if you compare Zen+ to Zen2 which was also a process node + architecture enhanced, and result in 15% IPC difference.
Zen 3 achieved a higher IPC increase than Zen 2 on the same process. So, the process itself doesn't say much about IPC improvements. A smaller node just means more transistors on the same area. Which could be used to implement more logic to increase IPC. But it doesn't have to. We had a rumor about 29% IPC increase some time ago. AMD themselves hinted to more improvements than Zen 3. I think most people expect something like 20-25% on average. 18% would be indeed a little underwhelming. But who knows. Maybe that Chiphell guy saw numbers from a benchmark that's quite insensitive to IPC improvements. Then 18% would be quite decent. Or he doesn't have any clue at all.
 

nicalandia

Diamond Member
Jan 10, 2019
3,330
5,281
136
Some back of the napkin math. If the rumor about 18% IPC and 7% all core boost increase and 8.7% single core boost.
Cinebench r23
Single Core would be around 2140 (single core boost of about 5.35Ghz +18% IPC)
Multi Core would be around 36300 (mulit core boost of about 4.5Ghz +18% IPC)
This assumes pretty much perfect scaling with IPC and frequency (I know that is almost never a thing)

The 13900K will get the same CBR23 MT numbers if my Napkin math does not fail me.
 

Saylick

Diamond Member
Sep 10, 2012
3,084
6,184
136
Didn't Moore's Law is Dead put out some rumor video about Zen 4 having a similar IPC jump from Zen 2 as the original Zen over Bulldozer? So if we take 40% as the number and Zen 3 being a 19% IPC gain, then that's a ~18% IPC gain for Zen 4 (1.19*1.18 = ~1.40). If we take 52% as the number, then Zen 4 is a 28% gain (1.19*1.28 = ~1.52). Seems reasonable to me that 18% IPC gain is credible. It's a little lower than I hoped for given that we have a new node, but it's not pathetic either.
 

eek2121

Platinum Member
Aug 2, 2005
2,904
3,906
136
Didn't Moore's Law is Dead put out some rumor video about Zen 4 having a similar IPC jump from Zen 2 as the original Zen over Bulldozer? So if we take 40% as the number and Zen 3 being a 19% IPC gain, then that's a ~18% IPC gain for Zen 4 (1.19*1.18 = ~1.40). If we take 52% as the number, then Zen 4 is a 28% gain (1.19*1.28 = ~1.52). Seems reasonable to me that 18% IPC gain is credible. It's a little lower than I hoped for given that we have a new node, but it's not pathetic either.

Has MLID ever gotten a thing right (regarding AMD) in his life that he didn't grab from legit leakers elsewhere?
 
  • Like
Reactions: CakeMonster

Saylick

Diamond Member
Sep 10, 2012
3,084
6,184
136
Has MLID ever gotten a thing right (regarding AMD) in his life that he didn't grab from legit leakers elsewhere?
Even a broken clock is right twice a day, so to answer your question: yes. :D

Edit: In all seriousness, did anyone leak out Zen 4C or Bergamo before he did? He called it Zen 4d (d for dense) at the time. I don't recall if the usual suspects on Twitter had dropped nuggets about Bergamo before he made a video about it.
 

Joe NYC

Golden Member
Jun 26, 2021
1,899
2,192
106
Even a broken clock is right twice a day, so to answer your question: yes. :D

Edit: In all seriousness, did anyone leak out Zen 4C or Bergamo before he did? He called it Zen 4d (d for dense) at the time. I don't recall if the usual suspects on Twitter had dropped nuggets about Bergamo before he made a video about it.

Yes, AdoreTV leaked it first:

 
  • Like
Reactions: Mopetar

eek2121

Platinum Member
Aug 2, 2005
2,904
3,906
136
Even a broken clock is right twice a day, so to answer your question: yes. :D

Edit: In all seriousness, did anyone leak out Zen 4C or Bergamo before he did? He called it Zen 4d (d for dense) at the time. I don't recall if the usual suspects on Twitter had dropped nuggets about Bergamo before he made a video about it.

Zen4c was "leaked" well before he ever mentioned it. It has had a few different names during its development. Search the forums, you can probably find a few mentions here. Zen 4d, Zen 4 refresh, etc. and more.

EDIT: also, apparently, he is a 15-minute drive from where I live. My trust in him is now absolutely zero. You can't run a YouTube channel dedicated to tech in an area devoid of tech. 😂
 

eek2121

Platinum Member
Aug 2, 2005
2,904
3,906
136
Yes, AdoreTV leaked it first:


I ignore you, however given another person's response, I need to inform you that the first mention that I am aware of regarding Zen4c (Zen 4 dense, Bergamo, Zen 4 compute, Zen 4 HD refresh, etc) was in February of 2020. The video you linked is over a year later.

EDIT: Proof here. That video was dated June, this article is dated March 1st: These leaked AMD Zen 4 server specs have us salivating for Ryzen 6000 | PC Gamer

It is likely @ExecuFix has tweeted about it long before then, and like I said...earliest that I saw was February of the following year. It may have even been mentioned earlier.
 

Attachments

  • 1644990194418.png
    1644990194418.png
    492 KB · Views: 25
Last edited:
  • Like
Reactions: Mopetar and Tlh97

RnR_au

Golden Member
Jun 6, 2021
1,675
4,079
106
Didn't Moore's Law is Dead put out some rumor video about Zen 4 having a similar IPC jump from Zen 2 as the original Zen over Bulldozer? So if we take 40% as the number and Zen 3 being a 19% IPC gain, then that's a ~18% IPC gain for Zen 4 (1.19*1.18 = ~1.40). If we take 52% as the number, then Zen 4 is a 28% gain (1.19*1.28 = ~1.52). Seems reasonable to me that 18% IPC gain is credible. It's a little lower than I hoped for given that we have a new node, but it's not pathetic either.
Cheese said this last year (as mentioned by gruffi above);
Now, I can’t say what is true and what is an over-exaggeration, however I was told from a trusted source that a Genoa engineering sample (Zen 4 server chip) was 29% faster than a Milan (Zen 3) chip with the same core config at the same clocks.

MLID in a summary claimed at least 20% IPC gain over Zen 3.

TSMC N7 to N5p is >20% performance improvement at iso-power and we don't know what additional sekret ingredients TSMC has added to AMD's special edition of N5.

Some small power saving from an IO die being at N6 rather than GloFo silicon? But perhaps any of the savings are used up by DDR5 requirements.

It should be a kickarse product!
 
  • Like
Reactions: Tlh97 and Saylick

eek2121

Platinum Member
Aug 2, 2005
2,904
3,906
136
Cheese said this last year (as mentioned by gruffi above);

MLID in a summary claimed at least 20% IPC gain over Zen 3.

TSMC N7 to N5p is >20% performance improvement at iso-power and we don't know what additional sekret ingredients TSMC has added to AMD's special edition of N5.

Some small power saving from an IO die being at N6 rather than GloFo silicon? But perhaps any of the savings are used up by DDR5 requirements.

It should be a kickarse product!

February of last year, mind you.

"Zen 4 is what a lot of people are waiting for, and, if the info I have is accurate, that wait will prove to be even more worth it. It is important to note that the one common thread in all Zen 4 chatter I have heard is resounding positivity. From IPC gains over 25%, a total performance gain of 40%, and even possibly (finally) 5GHz all-core thanks to the new (full node) N5 fabrication at TSMC! Now, I can’t say what is true and what is an over-exaggeration, however I was told from a trusted source that a Genoa engineering sample (Zen 4 server chip) was 29% faster than a Milan (Zen 3) chip with the same core config at the same clocks. Factor this in with what I have heard about the possible clock gains that N5 will enable over N7 and Zen 4 sounds like it is going to be a monster of a CPU."

EDIT: Zen4c in 2020: amd genoa 96 192 until:2020-12-31 - Twitter Search / Twitter) I will try to pull some earlier links tomorrow. If you heard it from MLID or most other YouTube "leakers", you likely found out about it last!
 
Last edited:

Joe NYC

Golden Member
Jun 26, 2021
1,899
2,192
106
I ignore you, however given another person's response, I need to inform you that the first mention that I am aware of regarding Zen4c (Zen 4 dense, Bergamo, Zen 4 compute, Zen 4 HD refresh, etc) was in February of 2020. The video you linked is over a year later.

EDIT: Proof here. That video was dated June, this article is dated March 1st: These leaked AMD Zen 4 server specs have us salivating for Ryzen 6000 | PC Gamer

It is likely @ExecuFix has tweeted about it long before then, and like I said...earliest that I saw was February of the following year. It may have even been mentioned earlier.

That article says nothing about / related to the discussion. Nothing on Zen4c / Zen4d or Bergamo. It refers to a tweet by ExecutableFix, who just says 96 core is the top end for Genoa (maxed out), clearly not being aware of Zen4c / Zen4d or Bergamo.

Aside from Jim at AdoreTV being first to mention 128 core, I don't know who was the first to mention the code name Bergamo, but the first one to mention the new core, Zen4d was Charlie D, in paywalled article.

That paywalled article was published on October 26, 2021. So, you are off by a year and and a half in your recollections.
AMD's Bergamo is a very interesting CPU - SemiAccurate
 
Last edited:

Carfax83

Diamond Member
Nov 1, 2010
6,841
1,536
136
"Zen 4 is what a lot of people are waiting for, and, if the info I have is accurate, that wait will prove to be even more worth it. It is important to note that the one common thread in all Zen 4 chatter I have heard is resounding positivity. From IPC gains over 25%, a total performance gain of 40%, and even possibly (finally) 5GHz all-core thanks to the new (full node) N5 fabrication at TSMC! Now, I can’t say what is true and what is an over-exaggeration, however I was told from a trusted source that a Genoa engineering sample (Zen 4 server chip) was 29% faster than a Milan (Zen 3) chip with the same core config at the same clocks. Factor this in with what I have heard about the possible clock gains that N5 will enable over N7 and Zen 4 sounds like it is going to be a monster of a CPU."

This could be interpreted in so many ways. I'm no engineer or industry professional, but it really does appear to me that IPC is a nebulous concept which is difficult to measure properly from one architecture to another. According to Intel, Golden Cove has 19% greater IPC than Cypress Cove, but in many workloads and apps Golden Cove is much faster. I've also seen several forum members claim that Golden Cove's IPC advantage over Zen 3 is in the single digit range, which is crazy to me because in several workloads, Golden Cove straight up destroys Zen 3 by margins I haven't seen in years when it comes to CPU performance.

So the question is, are Zen 4's reputed IPC gains a range, or an average. If it's the former, then that won't be very impressive you ask me but if it's an average, then it certainly will be. As for what he says about Genoa, a lot of that could be due to DDR5's bandwidth. I'm not trying to downplay Zen 4 as I'm sure it will be a really good CPU, but I think there's too many here inserting their own confirmation bias into rumors about Zen 4's IPC gains, which are subject to interpretation.
 
  • Haha
Reactions: Kaluan