Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[Joe NYC]

Spare 7nm capacity? Then I would very much like them to ramp up RDNA2 production...

From the chart I posted, TSMC sold less on N7 node than previous quarter. So, from that, my assumption is that TSMC did not sell out 100% of N7.

But that is only an assumption. There may be more to the story, but idiot analysts did not ask. When one listens to the Investor calls (and I listen to AMD, Intel and TSMC), one thing that emerges is that as far as the financial analysts - they are not sending us their best.

 

[desrever]

They could make a HEDT platform with a new IOD. 4 memory channels and up to 32 cores. Which is basically the perfect in between of the mainstream desktop and the Epyc server platforms. Would even be good target for some server platforms that really only need 16-32 cores and don't need 8 channel memory.

I do think AMD is going to be engineering limited to make this a real platform tho. There is just way too many things they could do with 3d stacking and everything refreshing on Zen4. There will also likely be console refreshes coming down the line soon after zen 4 as well and also xilinx merger will likely result in engineering projects that unifies their platforms.

 

[DisEnchantment]

From the chart I posted, TSMC sold less on N7 node than previous quarter. So, from that, my assumption is that TSMC did not sell out 100% of N7.

That's is revenue, not volume. It indicates 7nm family (N6/7/7+ etc) are getting much cheaper while 5nm family is still expensive.
Volume wise N7 is in excess of 200k wpm compared to less than 80k-100k wpm of N5. 11 fab units of N7 vs 3 fab units of N5.

 

[Doug S]

From the chart I posted, TSMC sold less on N7 node than previous quarter. So, from that, my assumption is that TSMC did not sell out 100% of N7.

But that is only an assumption. There may be more to the story, but idiot analysts did not ask. When one listens to the Investor calls (and I listen to AMD, Intel and TSMC), one thing that emerges is that as far as the financial analysts - they are not sending us their best.

That's not necessarily a valid assumption. There are plenty of other possible reasons for that.

1) scheduled price drops as N7 matures / is further depreciated
2) price increases that affect customers differently (i.e. already paid, already signed contract, etc.)
3) shorter quarter (i.e. 13 vs 14 weeks)
4) how their accounting works (i.e. if a customer prepays or pays late how is that reflected)
5) holiday/covid shutdowns

I'm sure others can think of more...

 

[Mopetar]

If they just sliced the Genoa IOD into 4 quadrants it is possible, each quadrant of the Genoa IOD has 3 UMCs.

Seems excessive for a desktop IO die. It also makes is hard to square with the rumors that the Zen 4 IO die would contain a very minimal iGPU. That's not something that splits into quadrants at all without a lot of redundancy or several quadrants that completely lack those parts. It also doesn't really explain why it would have 3 memory channels.

I think what he's saying is that AMD could simply design a new IO die with an extra memory channel that handles 3 CCD SKUs if they wanted to make 24 core desktop products in the future.

The number of memory channels (or other IO) isn't dependent on the number of CCDs at all. It's however much they put on the IO die. There are Threadripper parts that only have 2 CCDs but still have 8 memory channels and the full amount of PCI lanes because the IO die has those connections independent of how many CCDs are actually connected. Just like the Zen 3 desktop parts all have dual channel memory and 24 PCI lanes regardless of whether it's a one or two chiplet CPU.

 

[Saylick]

The number of memory channels (or other IO) isn't dependent on the number of CCDs at all. It's however much they put on the IO die. There are Threadripper parts that only have 2 CCDs but still have 8 memory channels and the full amount of PCI lanes because the IO die has those connections independent of how many CCDs are actually connected. Just like the Zen 3 desktop parts all have dual channel memory and 24 PCI lanes regardless of whether it's a one or two chiplet CPU.

Agreed, but it works when the IO die is overengineered compared to how much compute the SKU needs to support. Currently, the minimum number of memory channels per CCD is 1:1. It can be as high as 4:1 like in your example with Threadripper, but it shouldn't go lower than 1:1. If AMD make a 3 CCD SKU, I'd be surprised if they stick with 2 memory channels unless one or both of the CCDs use cores that simply need less bandwidth, but I don't think that will be the case. Therefore, if there's 3 CCDs, I'd expect 3 memory channels.

 

[eek2121]

Pretty much. You can set a 5900X to effectively unlimited PBO and it won't boost that high except under sub-zero cooling. N7 just won't go there.

I have tested my 5950X locally with PBO and have noticed that raising the limits helps with multicore workloads a lot. With one task (compiling a large software project) I saw a 22% decrease in the time it took to compile.

That is why I ask.

 

[DrMrLordX]

I have tested my 5950X locally with PBO and have noticed that raising the limits helps with multicore workloads a lot. With one task (compiling a large software project) I saw a 22% decrease in the time it took to compile.

That is why I ask.

Okay, but how much power did it draw during that task?

 

[biostud]

They could make a HEDT platform with a new IOD. 4 memory channels and up to 32 cores. Which is basically the perfect in between of the mainstream desktop and the Epyc server platforms. Would even be good target for some server platforms that really only need 16-32 cores and don't need 8 channel memory.

You do know of the Threadripper platform?

 

[Markfw]

You do know of the Threadripper platform?

@desrever Yes, there is a 4 channel and an 8 channel variant, both have been for sale for years. See my signature.

 

[Saylick]

I don't know what Pat is smoking but I want some.
https://www.tomshardware.com/uk/new...d-is-in-the-rear-view-mirror-after-alder-lake



Pat is going to be in for a rude awakening when Zen 4 launches later this year.

Not exactly new news, but anyways, what were you saying Pat about that rear mirror?

https://twitter.com/x/status/1483506634898882560

 

[CHADBOGA]

You are completely ignoring power consumption. Also the 5900X beats the 12900K in many benchmarks, including gaming (Civ 6, for example).

I'm using this review as my guide. https://www.techpowerup.com/review/intel-core-i7-12700k-alder-lake-12th-gen/

 

[Markfw]

I'm using this review as my guide. https://www.techpowerup.com/review/intel-core-i7-12700k-alder-lake-12th-gen/

Why do you keep pushing Alder lake in a Zen 4 thread ?

You might want to post this elsewhere, where it is on-topic.

Not only that, it is not as good as Zen 3 !!! From the conclusion:

• New LGA1700 motherboards required
• Some workloads get scheduled onto wrong cores
• Energy efficiency worse than AMD Zen 3
• No CPU cooler included
• Manual overclocking not worth it

 

[CHADBOGA]

Why do you keep pushing Alder lake in a Zen 4 thread ?

You might want to post this elsewhere, where it is on-topic.

Not only that, it is not as good as Zen 3 !!! From the conclusion:

• New LGA1700 motherboards required
• Some workloads get scheduled onto wrong cores
• Energy efficiency worse than AMD Zen 3
• No CPU cooler included
• Manual overclocking not worth it

I was initially responding to this post in this thread which referenced desktop marketshare https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-7000.2571425/post-40678754

And how is it not as good as Zen 3?

The conclusion also stated :

• Much better price/performance than Core i9-12900K, Ryzen 5800X, and Ryzen 5900X
• Good energy efficiency

 

[Saylick]

Why do you keep pushing Alder lake in a Zen 4 thread ?

You might want to post this elsewhere, where it is on-topic.

I was initially responding to this post in this thread which referenced desktop marketshare https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-7000.2571425/post-40678754

My bad, guys. Should've posted that quote from Pat in the Alderlake thread, but I figured since he directed his remarks at the competition, I put it in this thread instead.

 

[Markfw]

I was initially responding to this post in this thread which referenced desktop marketshare https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-7000.2571425/post-40678754

And how is it not as good as Zen 3?

The conclusion also stated :

• Much better price/performance than Core i9-12900K, Ryzen 5800X, and Ryzen 5900X
• Good energy efficiency

So good energy efficiency, but not as good as Zen 3.

So, they contradict themselves... Well, lets bring this up in the appropriate forum.

 

[desrever]

@desrever Yes, there is a 4 channel and an 8 channel variant, both have been for sale for years. See my signature.

Those do not use a new IOD tho. They are just repurposed Epyc chips. They physically still have 8 channel memory, just enable/disabled on the platform as well as 8 chiplets on the actual package. It's a waste of silicon to cut them down and sell them at HEDT prices unless they can't sell them as Epyc. There is a reason threadripper is still stuck at zen2 while zen 3 has been out for more than a year.

A real HEDT processor with a new IOD would cut the need for all the extra silicon and probably make selling to HEDT not a financial burden for AMD.

 

[Markfw]

Those do not use a new IOD tho. They are just repurposed Epyc chips. They physically still have 8 channel memory, just enable/disabled on the platform as well as 8 chiplets on the actual package. It's a waste of silicon to cut them down and sell them at HEDT prices unless they can't sell them as Epyc. There is a reason threadripper is still stuck at zen2 while zen 3 has been out for more than a year.

A real HEDT processor with a new IOD would cut the need for all the extra silicon and probably make selling to HEDT not a financial burden for AMD.

I disagree. Its been proven something is different, the sockets even. Yes, they are EPYC chiplets, but they bin at a higher speed using more power. Thats why they are not EPYC chips.

And they are not a financial burden, AMD is selling every chip they can make, prioritizing EPYC at the top of the list due to margins. And as somebody else said, when Intel has no HEDT (essentially), why upgrade the platform ? They will get to it when they need to compete with Intel.

Oh, and I should know. I have 5950x chips, and I have Rome (the same generation, but EPYC), they Rome are slower and more expensive, but efficient. And I have a 1950x first gen threadripper, but its way less performance than the 5950x. I have 2990wx 32 core, faster than my 7452 Rome, but again less efficient. They have something in every corner thats better than Intel, except recently, Alder lake is now the gaming king.... FOR NOW.

 

[desrever]

I disagree. Its been proven something is different, the sockets even. Yes, they are EPYC chiplets, but they bin at a higher speed using more power. Thats why they are not EPYC chips.

And they are not a financial burden, AMD is selling every chip they can make, prioritizing EPYC at the top of the list due to margins. And as somebody else said, when Intel has no HEDT (essentially), why upgrade the platform ? They will get to it when they need to compete with Intel.

Oh, and I should know. I have 5950x chips, and I have Rome (the same generation, but EPYC), they Rome are slower and more expensive, but efficient. And I have a 1950x first gen threadripper, but its way less performance than the 5950x. I have 2990wx 32 core, faster than my 7452 Rome, but again less efficient. They have something in every corner thats better than Intel, except recently, Alder lake is now the gaming king.... FOR NOW.

Obviously bins are different but the actual chips are the same. Unless something seriously fail, AMD should be able to bin all threadrippers into SKUs of Epyc. Initially they didn't have the high clock SKUs validated for Epyc gen 1, that and the low cost, lower adoption of the inital Epyc CPUs, threadripper allowed them to sell the chips as HEDT, they probably had some slack on Epyc gen 2 as the high frequency SKUs came later so they still allowed production of threadripper 2. Now, Epyc production eat every die that can be produced, there is no reason to sell threadrippers.

With no indication of AMD slowing down in servers, I doubt they will make threadripper zen 4 as even salvaged dies can be sold as lower tier Epyc SKUs. Making threadripper out of left over Epyc is just pointless unless AMD wants to subsidize their HEDT instead of server.

 

[Markfw]

Obviously bins are different but the actual chips are the same. Unless something seriously fail, AMD should be able to bin all threadrippers into SKUs of Epyc. Initially they didn't have the high clock SKUs validated for Epyc gen 1, that and the low cost, lower adoption of the inital Epyc CPUs, threadripper allowed them to sell the chips as HEDT, they probably had some slack on Epyc gen 2 as the high frequency SKUs came later so they still allowed production of threadripper 2. Now, Epyc production eat every die that can be produced, there is no reason to sell threadrippers.

With no indication of AMD slowing down in servers, I doubt they will make threadripper zen 4 as even salvaged dies can be sold as lower tier Epyc SKUs. Making threadripper out of left over Epyc is just pointless unless AMD wants to subsidize their HEDT instead of server.

All of this is conjecture. When you own AMD, then you can tell me what is going on. Until then, its just difference of opinion .

 

[Mopetar]

Those do not use a new IOD tho. They are just repurposed Epyc chips. They physically still have 8 channel memory, just enable/disabled on the platform as well as 8 chiplets on the actual package. It's a waste of silicon to cut them down and sell them at HEDT prices unless they can't sell them as Epyc.

Of course it's just the Epyc IO die. That's not surprising, it's just good reuse of existing parts instead of having to create a unique piece of silicon for just that market.

Obviously bins are different but the actual chips are the same. Unless something seriously fail, AMD should be able to bin all threadrippers into SKUs of Epyc.

Not all IO dies would be able to be used in an Epyc CPU. Since all of the Rome lineup has 8 memory channels and 128 PCIe lanes, a single defect in either part of an IO die would mean it couldn't be used for Epyc. Those IO dies used in Threadripper Pro almost assuredly could have been used for Rome, but by that point AMD was starting to move to Milan so there was less demand for those parts which meant that full dies could go to Threadripper parts as well.

With no indication of AMD slowing down in servers, I doubt they will make threadripper zen 4 as even salvaged dies can be sold as lower tier Epyc SKUs.

For the same reason as before they will have some number of IO dies with defects that prevent them from being used in Genoa CPUs.

 

[eek2121]

Those do not use a new IOD tho. They are just repurposed Epyc chips. They physically still have 8 channel memory, just enable/disabled on the platform as well as 8 chiplets on the actual package. It's a waste of silicon to cut them down and sell them at HEDT prices unless they can't sell them as Epyc. There is a reason threadripper is still stuck at zen2 while zen 3 has been out for more than a year.

A real HEDT processor with a new IOD would cut the need for all the extra silicon and probably make selling to HEDT not a financial burden for AMD.

Threadripper is not a “financial burden” for AMD. AMD has higher margins on these chips than they do on Ryzen. The IO dies come from Epyc, buyt they are dies with defects or dies that don’t meet power targets.

The reason Threadripper hasn’t been updated to Zen 3 is that they don’t have enough capacity. AMD can’t stop selling Zen 2 Threadripper because they have to support OEMs. This means that a Zen 3 Threadripper would eat into the availability of Ryzen. Ryzen is a high volume product with good margins, while Threadripper is a low volume product with great margins.

 

[DrMrLordX]

This means that a Zen 3 Threadripper would eat into the availability of Ryzen.

More like it would eat into the availability of EPYC.

 

[Hans de Vries]

If they just sliced the Genoa IOD into 4 quadrants it is possible, each quadrant of the Genoa IOD has 3 UMCs.

For instance, that was what they did with Vermeer IOD, it is a quadrant of the Milan IOD

View attachment 56173

In Milan
2x CCDs are connected to one switch attached to 2x UMCs, for closest hop. There is a repeaters from the switch to the next introducing additional hops.
This is how the SRAT table is being calculated

Genoa will have 3x CCDs connected to one switch attached to 3x UMCs.
But of course it is just a possibility, and they might not reuse a portion of the IOD from Genoa at all like they did with Milan/Rome.
It does not mean that they will use 3x UMCs but just that they are there for use if they so desire.

View attachment 56174

For that matter I would love to see the same 32 bit CXL-GenZ bus on AM5 that Genoa has.

That's 256 Gbyte/s full duplex memory bandwidth using PCIe-5 signaling, upgradable to 512 GigaByte/s with PCIe-6 PAM4 signaling.

PCIe-6 will replace Dram specific busses like PCIe-3 has done for SSD's

 

[Ajay]

PCIe-6 will replace Dram specific busses like PCIe-3 has done for SSD's

😯. Please tell us more!