Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[DisEnchantment]

AMD use an enhanced 5nm process dubbed N5P, hence the better numbers than on TSMC s slide wich display the vanilla 5nm perfs.

Fair point.
Anyhow I doubt we will really know (it is not a comparison between N5 vs N7 as advertised by TSMC, it's a comparison between the results AMD got when they deployed the two process, AMD never really got those proclaimed gains from N7 either. AMD optimized N7 a lot for frequency)

 

[Mopetar]

Why does it have to be baked and n to some monolithic die or used for mobile? It sounds like the obvious use for Zen 4c is Threadripper.

 

[DisEnchantment]

Why does it have to be baked and n to some monolithic die or used for mobile? It sounds like the obvious use for Zen 4c is Threadripper.

They could reuse a chunk of the physical design/layout from Bergamo for Mobile (could reduce lead time/V&V efforts) Because they are both efficiency oriented and "cache optimized".

I wonder if there will be a smaller socket than LGA 6096 for HEDT. That socket is humongous and seems expensive.

 

[DrMrLordX]

@Abwx

Are we sure AMD will be using N5P? AMD never used N7+ or N7P.

I'm not saying that Zen 4c CCDs will be used in mobile but that the Zen 4c design and process will be used.

. . . maybe. I'm not entirely clear on what will differ between Zen4/Genoa and Zen4c/Bergamo besides the L3 per core.

 

[eek2121]

16 core SKUs require 2 fully working CCD's, 12 core SKUs only require 2 CCD's with 2 cores not working - this is why the 3950X came out months after the initial release of Zen2/Matisse.

So I'd say if 12 core SKUs are available at launch then 6 core SKUs will be too.

At least until 12C or 16C CCD's become a thing.

That was likely due to yields. You will note they did not do that for Zen 3.

@Abwx

Are we sure AMD will be using N5P? AMD never used N7+ or N7P.



. . . maybe. I'm not entirely clear on what will differ between Zen4/Genoa and Zen4c/Bergamo besides the L3 per core.

AMD will likely use something customized like they do with N7.

 

[DisEnchantment]

Are we sure AMD will be using N5P? AMD never used N7+ or N7P.

AMD will likely use something customized like they do with N7.

I think we will never know what exactly it is.
N7 used by AMD in Zen2/3 is HD cells but with a whole lot of BEOL optimizations, parasitics optimizations, more metal layers, etc but that is about all we have in public domain.
Density is a paltry 51MTr/mm2 but it clocks all the way to 5 GHz in Zen 3 obviously trading off lots of efficiency in the process.

So using TSMC's marketing info for N5 gains to be used by AMD is not going to tell us much.

 

[Abwx]

@Abwx

Are we sure AMD will be using N5P? AMD never used N7+ or N7P.



. . . maybe. I'm not entirely clear on what will differ between Zen4/Genoa and Zen4c/Bergamo besides the L3 per core.

Dunno what they were using at 7nm but from AMD slide at 5nm they can pack two Zen 3 at same frequency and power than 7nm, If anything with the perf rumours the next DT chips will yield 45-50% higher perf at same TDP.

 

[IronLynx]

Besides doubling L2, adding AVX512 any info in L1? Remain the same(as Zen3)?

 

[Tarkin77]

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

THICC BOI!

 

[MadRat]

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

THICC BOI!

That is amazing. A fully decked out processor, with all 12 modules, will have monster on-chip cache. This design just makes a lot of sense. But 400W per socket I would think has to be a challenge. This is no 1U part.

 

[xilli_fiberbit]

Besides doubling L2, adding AVX512 any info in L1? Remain the same(as Zen3)?

L1 size is unchanged :

https://twitter.com/x/status/1454387986326556672

 

[Ajay]

Dunno what they were using at 7nm but from AMD slide at 5nm they can pack two Zen 3 at same frequency and power than 7nm, If anything with the perf rumours the next DT chips will yield 45-50% higher perf at same TDP.

Well, clearly I got the wrong impression from watching Lisa Su, versus what was on the slides. Still, it will be pretty exciting if Raphael's gains over Vermeer are inline with the rumors you are seeing . Too bad I told my wife I'd be able to stay with my current system (AM4) for 5 years. And I built at the end of 2019 .

 

[eek2121]

Well, clearly I got the wrong impression from watching Lisa Su, versus what was on the slides. Still, it will be pretty exciting if Raphael's gains over Vermeer are inline with the rumors you are seeing . Too bad I told my wife I'd be able to stay with my current system (AM4) for 5 years. And I built at the end of 2019 .

Thankfully, my PC makes me money. 😂

I do trust AMD enough not to completely mislead everyone, so I suspect that slide is close to the truth. That would also explain why Lisa mentioned Zen 4 running at 5 ghz all core. With N5 they were able to make drastic improvements compared to their customized N7 process.

 

[DisEnchantment]

This 16-core AMD EPYC Zen4 "Genoa" processor leak comes with an X-ray - VideoCardz.com

AMD EPYC Zen4 “Genoa” 16-core processor with 3.7 GHz boost and DDR5/PCIe Gen5 support spotted Following a leak from last week, we have received a new set of photos featuring AMD’s yet unreleased EPYC processor. AMD server CPU stack is about to get even more interesting as the company is set to...

videocardz.com

THICC BOI!

Very interesting pic there. I hope Dylan is right on the packaging tech. Either that or I just saved myself from another subscription. (But if he is right I will sub him and pay)
Because, I cannot see any hint of any fancy packaging tech in use there, granted the grey structure obscured everything else. I cannot even see the LGA pattern.

 

[Zepp]

I think it's possible that the market segment currently served by 4c and 6c SKUs could be completely taken over by Rembrandt and its successors. Not gonna say it's absolutely going to happen, but it could.

What if AMD made a successor for Dali to cover the ultra-low end mobile to low end desktop range. SKU's from 2c4t to 4c8t. Everything below what Rembrandt covers.

something like a quad core base die on at least 7nm with at least zen2 cores or newer. Basically a modern super efficient Raven Ridge.

 

[eek2121]

What if AMD made a successor for Dali to cover the ultra-low end mobile to low end desktop range. SKU's from 2c4t to 4c8t. Everything below what Rembrandt covers.

something like a quad core base die on at least 7nm with at least zen2 cores or newer. Basically a modern super efficient Raven Ridge.

AMD likely won’t produce anything new on 7nm. They DID just renew the GloFo WSA, however…

 

[SteinFG]

this pic is like 140x200 pixels, that's why lga grid is invisible.

 

[turtile]

@Abwx

Are we sure AMD will be using N5P? AMD never used N7+ or N7P.

. . . maybe. I'm not entirely clear on what will differ between Zen4/Genoa and Zen4c/Bergamo besides the L3 per core.

I think AMD uses custom designs. I assume that this resulted in the N7 + N5 HPC variants. The 3xxx series moved to a higher-performance version of N7 before 5xxx used it.

Lisa only mentioned changes with cache (I don't think they will use less) and a more dense/energy-efficient process.

I'm more curious about the way that they will fit 12 memory channels in with 128 cores since it doesn't divide evenly. My only guess is creating a group of 32 cores connected to 3 channels on the I/O die. Or maybe that doesn't matter?

 

[Doug S]

That is amazing. A fully decked out processor, with all 12 modules, will have monster on-chip cache. This design just makes a lot of sense. But 400W per socket I would think has to be a challenge. This is no 1U part.

There are already data centers designed for and utilizing 20kW or more per rack, which is around 500W per U. Once you exceed 25kW per rack you either can't have racks at the same density (i.e. alternate with lower TDP racks performing other functions, or have wider aisles or something) or you need to incorporate water cooling. So ~600W per U appears to be the limit for a full 42U config in a standard datacenter floorplan using forced air cooling, which looks like what AMD is targeting in a few years.

 

[Ajay]

There are already data centers designed for and utilizing 20kW or more per rack, which is around 500W per U. Once you exceed 25kW per rack you either can't have racks at the same density (i.e. alternate with lower TDP racks performing other functions, or have wider aisles or something) or you need to incorporate water cooling. So ~600W per U appears to be the limit for a full 42U config in a standard datacenter floorplan using forced air cooling, which looks like what AMD is targeting in a few years.

Maybe foretelling a move to chilled liquid as with HPC clusters??

 

[Mopetar]

Maybe foretelling a move to chilled liquid as with HPC clusters??

Better yet just dunk it all in oil: https://www.datacenterknowledge.com...oling-how-practical-is-dunking-servers-in-oil

 

[moinmoin]

Better yet just dunk it all in oil: https://www.datacenterknowledge.com...oling-how-practical-is-dunking-servers-in-oil

Or put it close to ice or underwater.

 

[BorisTheBlade82]

For a while I have been asking myself if someone harvests that thermal energy and converts it back to electricity. I mean, besides the processing a chip basically wastes 99% of its energy input. Even if they could harvest only 10% to 20% as electricity that would be worthwhile. And some fluid for thermal transfer seems to be the obvious starting point.

 

[Saylick]

For a while I have been asking myself if someone harvests that thermal energy and converts it back to electricity. I mean, besides the processing a chip basically wastes 99% of its energy input. Even if they could harvest only 10% to 20% as electricity that would be worthwhile. And some fluid for thermal transfer seems to be the obvious starting point.

A few courageous people have tried in the past to use the heat generated from a processor for something useful, but alas their efforts didn't make an everlasting impact... Oh, what could have been...

 

[Mopetar]

Or put it close to ice or underwater.

In the future they'll put the data centers in space. Good access to cheap solar power and no worries about cooling. That and no one can hear the poor techs that have to manage it scream.