Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

@scineram that is now how the voting works here.

 

[Kepler_L2]

Yes Zen 4/Raphael is likely Ryzen 7xxx on AM5.

Rembrandt could vert well be Ryzen 6xxx H/HX/G/U as it is due at the same time as Zen3D in the first half of next year.

For sure the jump from Vega to RDNA2 and a 50% CU count increase does warrant a serious jump in nomenclature, but I doubt that they would do this as they have seemingly transitioned to a more synergistic nomenclature across their respective CPU/APU lines so that customers are less confused about which SKU came out in which year vs the previous arrangement with APUs being named as if they were a year ahead.

More likely Phoenix will be the main monolithic Ryzen 7xxx APU if the rumours are correct and it shares Zen 4 cores with Raphael, I just hope it doesn't take as long for RDNA3 to filter into APUs as RDNA2 did.

Most likely Zen3D = 6000, Rembrandt = 7000 and Raphael/Phoenix = 8000

 

[eek2121]

Most likely Zen3D = 6000, Rembrandt = 7000 and Raphael/Phoenix = 8000

HP Changed their page I see. They were saying Ryzen 7000 series with Radeon Graphics. Now they say Ryzen 7 5000 series graphics. Guess we can throw that one out the window.

 

[Kepler_L2]

HP Changed their page I see. They were saying Ryzen 7000 series with Radeon Graphics. Now they say Ryzen 7 5000 series graphics. Guess we can throw that one out the window.

Still I think that scheme makes more sense. Zen3D is a bigger performance jump than Zen+ so it makes sense to be a new series rather than "5950X3D" or whatever, Rembrandt is on a new platform so it should not be same series as Zen3 despite the core being the same, and of course Zen4 will be a new series as well.

 

[andermans]

Still I think that scheme makes more sense. Zen3D is a bigger performance jump than Zen+ so it makes sense to be a new series rather than "5950X3D" or whatever, Rembrandt is on a new platform so it should not be same series as Zen3 despite the core being the same, and of course Zen4 will be a new series as well.

I think 6000 for Rembrandt actually makes sense, since mobile is always a different platform.

 

[Kepler_L2]

I think 6000 for Rembrandt actually makes sense, since mobile is always a different platform.

But Rembrandt will be released for AM5, so having Ryzen 6000 on both AM4 and AM5 would be very confusing.

 

[jamescox]

The rumors say? 🙂 This is all out in the open with extreme detail for months..

https://twitter.com/x/status/1427612246411292672

View attachment 52061


View attachment 52062

Yeah, I haven’t had too much time lately to read up on things. The point is, SP5 is even larger than SP3. Routing all of the serdes from a monolithic and rather small IO die will be an interesting problem, especially at pci-e 5 link rates, but I don’t expect that to make a serdes solution impossible as the previous poster seemed to be implying. I have wondered if a more distributed solution would be better, such as something with 4 modular IO die segments that could be connected with serdes with the IO die to cpu chiplet being embedded silicon. It seems certain that initial Genoa is all serdes still, but possibly with some special sauce. Having stacked L3 right from the start may reduce serdes traffic significantly, so that might be a big part of the solution. Would be nice to get some HBM cache local to each chiplet on some variants also.

 

[jamescox]

Zen4 and Zen5 should use the same packages. (Just like Zen...Zen3)
Most likely with the same CCD and IO die arrangements in the packages as well.

I would expect:

Zen4 ---> Zen5

(1) General use of PAM4 for the SERDES so:
- PCIe-5 --> PCI-6 doubles the bandwidth using the same frequency but 2 bit instead of 1 bit per clock edge.
- XGMI3 --> XGMI4 doubles the bandwidth between the IO die and the CCD's using the same number of pins

(2) Doubling the number of cores for each CCD's is enabled by doubling the SERDES bandwidth.
- 16 cores per CCD
- The same number of serdes IO lines
- L3 VCache in increments of 128 MB per die

View attachment 52102

The serdes blocks moved from the middle of the die on Zen 2 to the edge of the die on Zen 3 due to the single, 8 core CCX. This makes me wonder if there will be a 16 core CCD Zen 4(+) variant with two 8-core CCX on one die. That would allow for 128-core with only 8 die. For Zen 5 that might then go to a native 16-core CCX, although that might be accomplished by having 2, 4, or perhaps even 8 cores sharing a large L2 cache and then the whole 16 core CCX sharing a large, probably stacked L3 cache. That would allow for some interesting products with disabled cores. Throwing a massive L2 cache at a single core can perform exceptionally well. That allows them to target a wide range of market segments with a single device.

 

[jamescox]

600W for 256 cores wouldn't be that much. That is something like 2.4W per core, while Milan @ 225W is almost 4W per core (IO is included in this number so don't take this closely. Just saying this isn't crazy much for that many cores)

I am curious whether we will see a gpu on package with SP5, or at least some HPC versions of SP5 processors. It seems to make a lot of sense, but the power consumption for that might be even higher than 600 W. With the 6 nm IO die and power improvements from 5 nm cpu chiplets, the power consumption for the same number of cores could be significantly lower, except it may have significantly more SRAM cache (don’t know if that will increase or reduce power) combined with much more floating point hardware. If most of the SRAM is stacked, then it can be on a more optimal process for SRAM, possibly more power efficient for the size. Higher hit rate means less off die communication. That should add up to more power for the cores and less for the “uncore”. The FP hardware should require wider interconnect that will burn more power. They may have a significantly improved performance / power for the actual floating point unit design though. I have wondered how much of the low level blocks can actually be reused between GPU and CPU floating point units. Hopefully we get some more data in November.

 

[soresu]

Rembrandt is on a new platform so it should not be same series as Zen3 despite the core being the same, and of course Zen4 will be a new series as well.

Bare in mind how long it took to be able to buy Renoir and Cezanne separate from a BGA NUC type SBC or laptop, and that was before fab capacity crunch went to crazy town.

They could still call it 6xxx series and not release it on AM4 by making initial production runs for BGA and laptop only.

Then when AM5 is released you have Rembrandt 6xxx as the cheapest CPU/APU solution for that platform.

Somewhat like Bristol Ridge on AM4 - only much, much better.

 

[HurleyBird]

I am curious whether we will see a gpu on package with SP5, or at least some HPC versions of SP5 processors.

Some form of display controller (much, much simpler than on a typical GPU) on the IOD wouldn't surprise me, while I'd expect any actual compute resources to go on chiplets.

 

[Timorous]

But Rembrandt will be released for AM5, so having Ryzen 6000 on both AM4 and AM5 would be very confusing.

Kinda but it would mean the 6k series is still all zen3 so not that bad. Could have 6xx0 for AM4 and 6xx5 for AM5.

Alternatively just have Zen4 parts be the 8k series, especially if it is a 20+% jump over zen3d.

 

[Krteq]

Dunno if it was posted but Hans de Vries came with this at TW :

https://twitter.com/x/status/1454025358022516736

I think we knew this since August when that Gigabyte leak occurred

Details on the Gigabyte Leak

Recently, a ransomware group leaked data from Gigabyte in an attempt to extort payment. That’s been well covered by other outlets (please everyone, secure your networks), so here we’re …

chipsandcheese.com

 

[Zepp]

Kinda but it would mean the 6k series is still all zen3 so not that bad. Could have 6xx0 for AM4 and 6xx5 for AM5.

Alternatively just have Zen4 parts be the 8k series, especially if it is a 20+% jump over zen3d.

Just rest assured that whatever makes the most sense will not be the name convention that is used.

 

[DisEnchantment]

AMD has no interested in any big.LITTLE hybrid approach, and we won't ever see that from them. What the patents when combined describe is essentially extending existing cores with additional functionality that, when completed, would be able to form another core. But the very point is that they will never be completed and never be accessible as stand alone cores, it will just be additional functionality to relieve the rest of the core from lower level work.

This btw. also shows a path to seamlessly integrating Xilinx FPGA functionality as part of the cores without having to rely on software support for making use of that.

https://twitter.com/x/status/1455174695502888964

Charlie seems to suggest something which we already discussed, AMD's approach to little cores will not be anything like Arm's big.LITTLE.
Unfortunately, I dont wanna pay 1K for a few articles to read a year.

 

[Thibsie]

Unfortunately, I dont wanna pay 1K for a few articles to read a year.

1K? Student is 100$

 

[moinmoin]

1K? Student is 100$

I guess some of us could apply as students of university studies for senior citizens...

 

[jamescox]

Some form of display controller (much, much simpler than on a typical GPU) on the IOD wouldn't surprise me, while I'd expect any actual compute resources to go on chiplets.

I wasn’t talking about integrating a GPU into the IO die. I was talking about placing an entire, large HBM-based GPU right on the package. That would allow much more direct access to DDR5 memory for the GPU since it would be using IFOP links (possibly many of them) to connect to the IO die. You would still need some cpu chiplets, either on the other side or stacked on top of the IO die. There has been rumors of such an HPC device going back years but it has not materialized. Some of the “infinity architecture” slides have shown AMD compute GPUs that might have up to 6 infinity fabric links for nearly fully connected system of up to 8 GPUs. The zen 4 IO die might have 12 IFOP links, 6 on each side.

 

[Thibsie]

I guess some of us could apply as students of university studies for senior citizens...

Charlie's student account is actually quite misnamed.
Student has nothing with being a student, it's just a less expensive account were not everything (but vast majority IMO) is open.
Anybody can open a student account, even my mum.

 

[Justinus]

Charlie's student account is actually quite misnamed.
Student has nothing with being a student, it's just a less expensive account were not everything (but vast majority IMO) is open.
Anybody can open a student account, even my mum.

The previous sentiment scales down to "paying $100 a year for a few articles".

 

[jpiniero]

Charlie seems to suggest something which we already discussed, AMD's approach to little cores will not be anything like Arm's big.LITTLE.
Unfortunately, I dont wanna pay 1K for a few articles to read a year.

Probably the Zen 4 core in Zen 5 thing.

 

[Thibsie]

The previous sentiment scales down to "paying $100 a year for a few articles".

I was expecting that but one has to admit this is quite different. It does not mean one likes paywall though.

 

[itsmydamnation]

Probably the Zen 4 core in Zen 5 thing.

The only way that makes sense is if the Zen5 core is a monster of all monsters that like if you deactivate 1/2 or 2/3rds of it you end up with a Zen4 core , otherwise just power/voltage gate and clock low in low power situations. The far better one was the Core that does the light work for an entire CCX and traps to the real core if the Core needs to be woken up to do real work.

 

[eek2121]

I think 6000 for Rembrandt actually makes sense, since mobile is always a different platform.

To me, The 6xxx series should consist of Rembrandt and Zen3D. 7xxx should be Zen 4 parts. As cute/awesome as some of the comments here are, that move is the most sensible one.

The serdes blocks moved from the middle of the die on Zen 2 to the edge of the die on Zen 3 due to the single, 8 core CCX. This makes me wonder if there will be a 16 core CCD Zen 4(+) variant with two 8-core CCX on one die. That would allow for 128-core with only 8 die. For Zen 5 that might then go to a native 16-core CCX, although that might be accomplished by having 2, 4, or perhaps even 8 cores sharing a large L2 cache and then the whole 16 core CCX sharing a large, probably stacked L3 cache. That would allow for some interesting products with disabled cores. Throwing a massive L2 cache at a single core can perform exceptionally well. That allows them to target a wide range of market segments with a single device.

From AMD’s public statements thus far, I wouldn’t expect larger CCX units with Zen 4 (before whatever the refresh is at least)

Charlie's student account is actually quite misnamed.
Student has nothing with being a student, it's just a less expensive account were not everything (but vast majority IMO) is open.
Anybody can open a student account, even my mum.

He is charging too much. Don’t let him fool you. One of my top subscription sites charges $5/mo and I have x,xxx subscribers. My niche is much smaller than his and I invest < 30 hours a month in that project.

He needs to come back down to earth.

 

[uzzi38]

https://twitter.com/x/status/1455174695502888964

Charlie seems to suggest something which we already discussed, AMD's approach to little cores will not be anything like Arm's big.LITTLE.
Unfortunately, I dont wanna pay 1K for a few articles to read a year.

If it's anything like what has been previously rumoured, then it's just that Zen4D is a modified Zen 4 core. As for how deep those modifications go we don't know, but cache sizes is probably one of those modifications.