Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[eek2121]

Right below the table it actually says that Type 2 will have OPNs with and without iGPUs.

Type 3 is Phoenix.

Also, I don't expect Rembrandt to launch on the desktop that late.

Phoenix is FP8…

EDIT: I get that the models match with leaks…

 

[uzzi38]

Phoenix is FP8…

EDIT: I get that the models match with leaks…

Mobile sockets =/= desktop sockets.

E.g. Raven Ridge and Picasso are FP5, RV2/Dali is also FP5 but also can be FT5 (I think?), Renoir/Cezanne are FP6.

 

[andermans]

How is it obvious?

References to a U and H part, but none to a G part. No references about a socketed version either.

I think that likely says more about the source of the leak (Laptop OEM team?) than the (non-)existence of the G part.

 

[Mopetar]

The vcache is not free. The additional wafer costs money, the stacking process costs money. Higher prices are going to be needed just to maintain margins and I think they want to go beyond that.

That's why I don't think we see Zen 3D as a full stack refresh. Instead there's one or two high-end premium products for desktop with most of the chips going into HEDT or even the server line where AMD can charge an even larger premium. The desktop CPU is just for bragging rights.

I already mentioned DDR5.

It's notable that AMD always stated AM4 will be supported through 2020. So AM5 relying on DDR5 but still not launched makes me think DDR5 is indeed the holdup there.

Isn't Intel launching with DDR5 support before AMD though? I think that's going to drive the market and actually help ensure there's more reasonable availability by the time AMD releases Zen 4.

Alder Lake will have faster single threaded and multithreaded performance than Zen 3 with the possible exception of the 5950X (though it may beat that chip as well). AMD absolutely needs every tool in it’s war chest. If we are lucky, Zen3D will help AMD catch up.

I think Intel may have a tough time consistently beating a 5950X and as long as AMD has that as a halo product they're fine. Even if it does get beat, they just need one Zen 3D chip to act as a new halo product.

Most people never buy the top-end chip, but for whatever reason a lot of people think that it somehow matters. AMD doesn't need Zen 3D to be widely available to retain any mindshare they've gained from being on top.

They aren't going to be making an $250 Zen 3D products though. They really don't even have any sub-$300 Zen 3 products as is outside of the 5600G.

 

[jpiniero]

That's why I don't think we see Zen 3D as a full stack refresh. Instead there's one or two high-end premium products for desktop with most of the chips going into HEDT or even the server line where AMD can charge an even larger premium. The desktop CPU is just for bragging rights.

There's always rebrands. Threadripper AFAIK isn't getting vcache (at least not for now). Only desktop and server.

 

[Abwx]

Seems that Zen 4 has 2 x 256b units for AVX512, not sure about the info, though..

https://twitter.com/x/status/1429420737211813892

https://twitter.com/x/status/1429435268663234566

 

[Joe NYC]

Seems odd to slot in a Zen3D product that probably won't launch in any appreciable volume until early next year that will be refreshed in under 12 months going by AMD's schedule.

Assuming a more optimistic launch of Zen 4 around this time next year then AMD is really giving that a short life as a product.

Given that AMD still has a lot of the product stack to fill in with Zen 3, it would be surprising if they launched these as anything other than some special Ryzen 5000 parts. Something similar to the XT parts that Zen 2 used as an update/refresh towards the end of the cycle.

So you take too pessimistic launch for Zen 3D and too optimistic launch for Zen 4 and the result does not make sense.

If you correct those two (too pessimistic on Zen 3D launch and too optimistic on Zen 4 launch) than thing start to make sense..

 

[Joe NYC]

Just lower prices on vanilla Ryzen 5000 series.

I think that will happen. Looking at the prices in the US at the Micro center, here are the current discounts:
5600x - $40
5800x - $100
5900x - $50
5950x - $80

5600G and 5700G are at full MSRP.

 

[moinmoin]

Isn't Intel launching with DDR5 support before AMD though? I think that's going to drive the market and actually help ensure there's more reasonable availability by the time AMD releases Zen 4.

Indeed.

In that regard I think it's telling that ADL seems to start with top-end SKUs only this year, chips that are as you rightly note a relative niche quantity wise. I get the feeling both AMD and Intel originally planned with higher availability of DDR5 this year already.

 

[Timorous]

They aren't going to be making an $250 Zen 3D products though. They really don't even have any sub-$300 Zen 3 products as is outside of the 5600G.

The 5600G uses more 7nm silicon than a 5600X-3Dnow! would.

Like I have said I can see Zen 3D being the 'budget' platform and Zen 4 being the premium platform for a while next year until DDR5 comes down in price.

 

[krumme]

With aprox 80mm2 die it seems to me zen3 was envisioned as a budget alternative for a compettitive landscape where Intel was far stronger.
On a depreciated platform meant for budget, they can now dump some cache on top and still be a viable compettitor not only at budget end. They are in a damn strong position to price this product and still have good margins whatever perf alderlake comes with.
I think the problem is the time right up before zen 5. Zen 5 is supposed to be same uplift as zen. Zen 4 will have a hard time with the alderlake facelift, as its new expensive platform where tco will be at least as high as Intel - io 6nm, ddr5, beefier mb for avx512.

 

[DisEnchantment]

With aprox 80mm2 die it seems to me zen3 was envisioned as a budget alternative for a compettitive landscape where Intel was far stronger.
On a depreciated platform meant for budget, they can now dump some cache on top and still be a viable compettitor not only at budget end. They are in a damn strong position to price this product and still have good margins whatever perf alderlake comes with.
I think the problem is the time right up before zen 5. Zen 5 is supposed to be same uplift as zen. Zen 4 will have a hard time with the alderlake facelift, as its new expensive platform where tco will be at least as high as Intel - io 6nm, ddr5, beefier mb for avx512.

The perception of AMD changed with the times and if performance is there, they can command the price they see fit, see 5950X.
Based on leaks from reputable twitter individuals, a conservative estimate of a bump of 30% more MTr and a healthy reduction of 15-20% power at iso transistor perf (considering the fact that N7 transistor perf is already high, touching 5GHz) are quite significant.
If the same design and implementation teams don't falter, not only will they have so much more silicon to work with (30%+ more), they will have much more power headroom, (20%+ more power from process for CCD and add to that the increased socket TDP and the savings from the N6 cIOD)
For reference, the Zen3 team delivered 19% IPC from 9% area gain (at iso power according to AMD)

Or if we put the other way around, if AMD discards the efficiency gain and just go with transistor perf, they have +30% more transistor perf from process, While not all of that will translate into CPU clock speed, assuming design is compatible they can start clocking the cores higher than 4GHz base

 

[Mopetar]

The 5600G uses more 7nm silicon than a 5600X-3Dnow! would.

Like I have said I can see Zen 3D being the 'budget' platform and Zen 4 being the premium platform for a while next year until DDR5 comes down in price.

I'm the end it's ~115 mm^2 vs. ~175mm^2 and ignoring the cost of the silicon for the IO die completely. Sure it wins if your only costs are 7nm wafers, but that's not the only cost and even though none of the others are as large as wafer costs all the extra little costs add up.

Cezanne is less complicated to package though and that's not even considering the extra step of bonding the extra cache to a Zen 3 chiplet. I assume there's a small failure rate with that process stage the wastes otherwise good silicon so that adds a bit of extra cost as do some of the other steps necessary for producing Zen3D.

There's also no reason to make a 3D 5600X. I doubt we don't see any products that aren't using 8-core chiplets. No one will care about higher DDR5 prices because they'll already be paying a lot for the premium high-end CPU.

 

[Timorous]

I'm the end it's ~115 mm^2 vs. ~175mm^2 and ignoring the cost of the silicon for the IO die completely. Sure it wins if your only costs are 7nm wafers, but that's not the only cost and even though none of the others are as large as wafer costs all the extra little costs add up.

Cezanne is less complicated to package though and that's not even considering the extra step of bonding the extra cache to a Zen 3 chiplet. I assume there's a small failure rate with that process stage the wastes otherwise good silicon so that adds a bit of extra cost as do some of the other steps necessary for producing Zen3D.

There's also no reason to make a 3D 5600X. I doubt we don't see any products that aren't using 8-core chiplets. No one will care about higher DDR5 prices because they'll already be paying a lot for the premium high-end CPU.

If you have 3 wafers you can make around 840 cezanne dies or you can make 1314 zen3 dies and 1580 cache dies.

The most expensive cezanne SKU is $360 so 3 wafers gets you at most $302,400.

3 wafers of 5800X3D at current 5800X MSRP gets you $591,300.

Further 2 5600X3Ds would net $600 revenue vs $550 for a single 5900X3D.*

Do you really think that it costs AMD $220 extra per chip for the IO die + stacking vs Cezanne?

Edit to add: *obviously I am assuming here AMD lower existing SKU Msrps and use the current ones for the new Z3D skus but if performance is there the 3d skus could have higher pricing.

 

[Mopetar]

AMD already makes more from Zen chiplets without stacked cache added on. They're obviously making a certain amount of APUs to sell to Dell, HP, and other such companies. The argument for maximizing revenue is already there without v-cache. The argument is even greater for why AMD shouldn't make Radeon dies, but we're still getting some of those.

It's also a matter of production capacity. How many dies can TSMC process per day? There's more bottlenecks to a Zen3D that don't exist for other products so even if you were better off financially if every wafer went to Zen3D that may not actually be possible.

Even if it were you don't waste any chiplets on a $300 5600X when you can put them in server products that make several times the revenue. You might make a single high-end desktop part to act as a Halo product, but if your argument is that AMD can maximize money over APUs by making a Zen3D 5600X, that same argument says they shouldn't because there's even more money in making an Epyc CPU instead.

 

[Joe NYC]

It's also a matter of production capacity. How many dies can TSMC process per day? There's more bottlenecks to a Zen3D that don't exist for other products so even if you were better off financially if every wafer went to Zen3D that may not actually be possible.

That is actually wrong. The biggest bottleneck right now is substrate. Intel said they used up a lot of their reserves in Q2, and they don't worry about losing any market share in Q3 because the substrate is so depleted that in Q3, their competitor (AMD) is not going to face identical constraint, unable to increase production.

So this is actually perfect time to add V-Cache, to avoid the real bottleneck, which is substrate as of now. Adding V-Cache makes the product more valuable without using any additional substrate.

 

[Timorous]

AMD already makes more from Zen chiplets without stacked cache added on. They're obviously making a certain amount of APUs to sell to Dell, HP, and other such companies. The argument for maximizing revenue is already there without v-cache. The argument is even greater for why AMD shouldn't make Radeon dies, but we're still getting some of those.

It's also a matter of production capacity. How many dies can TSMC process per day? There's more bottlenecks to a Zen3D that don't exist for other products so even if you were better off financially if every wafer went to Zen3D that may not actually be possible.

Even if it were you don't waste any chiplets on a $300 5600X when you can put them in server products that make several times the revenue. You might make a single high-end desktop part to act as a Halo product, but if your argument is that AMD can maximize money over APUs by making a Zen3D 5600X, that same argument says they shouldn't because there's even more money in making an Epyc CPU instead.

Not all 6c parts will bin to EPYC or 5900X standards. If there are enough then you can chuck them or you can sell them.

 

[moinmoin]

The biggest bottleneck right now is substrate. Intel said they used up a lot of their reserves in Q2, and they don't worry about losing any market share in Q3 because the substrate is so depleted that in Q3, their competitor (AMD) is not going to face identical constraint, unable to increase production.

AMD actually has been talking about this very topic for quite some time, proactively investing in expansion of substrate production. An analyst's take from yesterday:
"we believe AMD is particularly well-positioned from a supply perspective given its strong track record, robust design win pipeline, and proactive supply chain management (e.g. co-investments in ABF substrate capacity)."

Goldman Reiteartes 'Buy' on AMD (AMD) Following Investor Meetings With Senior Executives

Goldman Sachs analyst Toshiya Hari reiterated a Buy rating on AMD (NASDAQ: AMD), which is also on the banks Conviction List, after hosting investor meetings with Mark Papermaster (CTO, EVP of...

www.streetinsider.com

 

[Joe NYC]

AMD actually has been talking about this very topic for quite some time, proactively investing in expansion of substrate production. An analyst's take from yesterday:
"we believe AMD is particularly well-positioned from a supply perspective given its strong track record, robust design win pipeline, and proactive supply chain management (e.g. co-investments in ABF substrate capacity)."

Goldman Reiteartes 'Buy' on AMD (AMD) Following Investor Meetings With Senior Executives

Goldman Sachs analyst Toshiya Hari reiterated a Buy rating on AMD (NASDAQ: AMD), which is also on the banks Conviction List, after hosting investor meetings with Mark Papermaster (CTO, EVP of...

www.streetinsider.com

Yes, AMD mentioned that even back in April, in their investor call, about their investment in substrate production - substrate production dedicated to AMD.

Intel was talking about their view of the market. It is possible that Intel is slightly underestimating AMD's ability to get substrate, but Intel is seeing such a crunch in Q3 for substrate that it will limit everyone.

Part of it is that even if though there is a good supply of CPUs, if other components for end product are missing, the product can't be sold...

Edit: thanks for the link, good info there.

 

[Mopetar]

That is actually wrong. The biggest bottleneck right now is substrate. Intel said they used up a lot of their reserves in Q2, and they don't worry about losing any market share in Q3 because the substrate is so depleted that in Q3, their competitor (AMD) is not going to face identical constraint, unable to increase production.

So this is actually perfect time to add V-Cache, to avoid the real bottleneck, which is substrate as of now. Adding V-Cache makes the product more valuable without using any additional substrate.

You misunderstand. It doesn't matter if AMD has loads of spare wafers to make tons of this because they're still limited by the slowest part of the process for manufacturing chiplets with v-cache. If they can only process 10 wafers worth of chiplets per day to bond the v-cache then producing more than 10 wafers per day of the cache just means it's piling up waiting for the the slowest production stage.

Do you think TSMC just magically has infinite machines to perform the 3D stacking and bonding process?

 

[Joe NYC]

You misunderstand. It doesn't matter if AMD has loads of spare wafers to make tons of this because they're still limited by the slowest part of the process for manufacturing chiplets with v-cache. If they can only process 10 wafers worth of chiplets per day to bond the v-cache then producing more than 10 wafers per day of the cache just means it's piling up waiting for the the slowest production stage.

Do you think TSMC just magically has infinite machines to perform the 3D stacking and bonding process?

I see what you mean, that the bottleneck is the stacking and bonding process. I though you meant that the wafer capacity is the bottleneck.

As far as TSMC capacity for 3D stacking, they are building a huge facility for that, their AP6 facility, and it should have been finished by May (based on the old article I read). That may have been, possibly phase 1.

Latest articles have H2 2021 as the completion date. But that may be for the expansion.

According to some articles, this one single facility will have capacity as much as the other 5 TSMC packaging facilities combined.

TSMC capacity should be way above of what AMD needs for Zen 3D. Like a drop in bucket. So, likely, it is not the bottleneck.

 

[Doug S]

As far as TSMC capacity for 3D stacking, they are building a huge facility for that, their AP6 facility, and it should have been finished by May (based on the old article I read). That may have been, possibly phase 1.

Sure but building a large facility still doesn't tell us what the capacity is, or who else may be using it. If Apple's next gen Mac chip uses 3D stacking, for example, that "huge" facility might be mostly dedicated to someone other than AMD. Then you have Nvidia who may see some use for this to allow using multiple smaller dies for improved yield, and who knows what the Bitcoin ASIC OEMs might want to do.

 

[jpiniero]

Intel was talking about their view of the market. It is possible that Intel is slightly underestimating AMD's ability to get substrate, but Intel is seeing such a crunch in Q3 for substrate that it will limit everyone.

Intel's Q3 forecast is pretty timid - it's higher than Q3 2020 but slightly lower than Q3 2019. Course some of that might be because Intel's ASPs are going down.

 

[Joe NYC]

Sure but building a large facility still doesn't tell us what the capacity is, or who else may be using it. If Apple's next gen Mac chip uses 3D stacking, for example, that "huge" facility might be mostly dedicated to someone other than AMD. Then you have Nvidia who may see some use for this to allow using multiple smaller dies for improved yield, and who knows what the Bitcoin ASIC OEMs might want to do.

I gave an example. According to one of the articles I read, the newest AP6 packaging facility would have capacity equal to sum of AP1 through AP5 combined.

That is, if I understood it correctly. Sometimes, Google Translated documents fall short of perfect clarity.

As far as I know, as of now, AMD is the leading partner of TSMC for SoIC, so no, nobody is jumping ahead of AMD in the near term. As in right now.

But others will certainly join the 3D stacking fun. That's what TSMC is counting on with such a big 3D packaging investment.

Also, after this AP6 facility, TSMC is adding another one in 2022. Perhaps TSMC wants to gain market share in all phases of packaging.

BTW, as far as other TSMC customers using 3D stacking (and packaging), it all depends on when they made the decision to go with 3D stacking, and from that point there is a considerable amount of time before the product is in full production.

 

[Vattila]

Sure but building a large facility still doesn't tell us what the capacity is, or who else may be using it. If Apple's next gen Mac chip uses 3D stacking, for example, that "huge" facility might be mostly dedicated to someone other than AMD.

V-Cache was developed by AMD and TSMC in deep collaboration. It is not an off-the-shelf technology. For the productization of the technology to make sense, TSMC is likely to have committed to providing the packaging capacity needed (alternatively, committed to license the required IP to enlisted 3rd-party OSAT companies). It is worth remembering that AMD and TSMC do a lot of work together to bring products to market (as TSMC does with other customers, I'm sure). And on supply commitment, remember, at the launch of AMD's EPYC 2, at the EPYC Horizon event September 2019, TSMC's Head of Global Marketing, Godfrey Cheng, stood on stage promising to provide ample supply:

"The reason why the ramp is such a critical element of a product is that with any product there is a life cycle." Cheng says, "If you cannot deliver a product within a certain timeframe where the demand is hot, we commit the cardinal sin of actually leaving demand on the table, and that’s not what we do."

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Since then, TSMC has shown the ability to provide way more capacity than initial projections from AMD. While AMD's financial model aims for 20% CAGR revenue growth, last year AMD started by forecasting 25%, adjusted down to 21% at the height of Covid-19 uncertainty, then up to 31%, then 41%, just to end at 45%, and they started this year at 37%, then adjusted up to 50%, and then further increased that to 60%. I am sure these forecasts are done knowing very well what TSMC can deliver. The rapid growth shows the substantial headroom AMD has had (so far, at least) in their supply agreement with TSMC.