Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[lobz]

I'm gonna say the same thing I did about the horrible SPR leak... don't read too much into this as well. We couldn't possibly know what base clock AMD will decide to end on, not to mention sustained freq and perf across various workloads.

 

[Markfw]

I don't get the picture.


64 C @ 2.45 on 7nm = 280W.
64 C @ 2.25 on 7nm = 220W.
64 C @ 2.25 on 5nm = 110W
96 cores on 5nm = 165W.
2X for AVX512 = 330W. ( accounting for 100% + for AVX512 and 50% for more cores. 110W>330W)

We have 400W here.

Maybe PCIe 5.0 is the culprit, but these numbers are high.

Where does it say that with everything else the same, just going from 7 to 5 nm= half the power ???? That seems insane.

 

[Saylick]

Where does it say that with everything else the same, just going from 7 to 5 nm= half the power ???? That seems insane.

It comes from this...

 

[Karnak]

"Power efficiency" includes the performance aspect as well, not just pure power consumption.

 

[DrMrLordX]

not to mention sustained freq and perf across various workloads.

Raphael is already bringing with it higher all-core clocks. Ramping up sustained clocks with a core count as high as 96c is going to come with a serious power penalty.

 

[Abwx]

"Power efficiency" includes the performance aspect as well, not just pure power consumption.

The slide is about the custom 5nm process and nothing else, no reference to uarches...

 

[Thibsie]

The slide is about the custom 5nm process and nothing else, no reference to uarches...

Yes but the slides exposes 2x tiles power efficiency NOT half power usage.

 

[Saylick]

"Power efficiency" includes the performance aspect as well, not just pure power consumption.

That's an interesting way to interpret the slide. I interpreted the slide as a node vs. node comparison, just like how TSMC or any other fab reports their node improvements, so this slide tells you that at similar logic complexity, AMD is able to get twice the density and either A) half the power at iso-clocks or B) 1.25x the clocks at iso-power.

I believe AMD are using N5P but with DTCO, so they are able to wring out a little bit more than what TSMC advertised.

 

[maddie]

That's an interesting way to interpret the slide. I interpreted the slide as a node vs. node comparison, just like how TSMC or any other fab reports their node improvements, so this slide tells you that at similar logic complexity, AMD is able to get twice the density and either A) half the power at iso-clocks or B) 1.25x the clocks at iso-power.

I believe AMD are using N5P but with DTCO, so they are able to wring out a little bit more than what TSMC advertised.
View attachment 65014

No need to interpret, it says so in the fine print. 5nm vs 7nm.

 

[moinmoin]

Is this good?

With many Zen chips higher TDP offers headroom to afford higher all core performance. Zen 4 may well be optimized to be capable of maxing out all cores without hitting previous walls, and introducing higher TDP levels may be the way to accommodate the new Ryzen and Epyc platforms to that capability.

 

[deasd]

Keywords : 'August 4' , 'unbeatable'

https://twitter.com/x/status/1551599088411545610

 

[coercitiv]

With many Zen chips higher TDP offers headroom to afford higher all core performance.

TDP determines base clocks, there's no escaping this. @maddie argues the base clocks from the EPYC 9664 leak don't match the TDP. Why that happens is too speculative for me atm.

 

[uzzi38]

There's SPR-SP for comparison, which are AVX512 enabled

QS(8470): 52C/112T, 2.0-3.7Ghz, 350wTDP
ES2(8490): 60C/120T, 1.7-3.4Ghz, 350wTDP

https://twitter.com/x/status/1542359388219793409

these specs he posted might be correct. but the benchmark he did is another story.


it makes me wonder whether the Raphael is AVX512 enabled or not. if yes, the clocks(5.5-5.7) are quite high, if the PPT power (230w) is just for the AVX512 specified situation....

Intel's rated base clocks are AVX2, Intel usually provides a seperate AVX512 base clock.

That being said, we do not know if base clock for Genoa will also include AVX512. We also do not know if these are final clocks. Also... 400W TDP? I'm pretty sure that's the max cTDP rather than the default TDP...

 

[moinmoin]

TDP determines base clocks, there's no escaping this.

Not sure if this is handled differently in the server space, but as long as PPT = TDP * 1.35, TDP effectively also sets the upper limit for all cores.

I'm pretty sure that's the max cTDP rather than the default TDP...

Also this.

 

[coercitiv]

Not sure if this is handled differently in the server space, but as long as PPT = TDP * 1.35, TDP effectively also sets the upper limit for all cores.

That's an indirect effect, TDP dictates base clocks first, anything else second. That's why I said "there's no escaping this".

Also this.

I'm pretty sure that's the max cTDP rather than the default TDP...

This is one very plausible explanation, although it's only one out of quite a few that make sense while not reflecting badly on Zen4 performance and efficiency. That's why I'd rather not speculate.

 

[moinmoin]

We have a precedence with the Ryzen x800X chips vs. x700(X) ones. The latter seem more efficient, but the former is higher priced so AMD opted to only offer the former in more recent gens. And the latter's behavior can still be restored on the former by using ECO mode or manually lowering PPT accordingly. To me 170W TDP on AM5 and 400W TDP on SP5 seem to be along that line of supersets that extend the headroom while including the lower TDP levels.

 

[uzzi38]

Not sure if this is handled differently in the server space, but as long as PPT = TDP * 1.35, TDP effectively also sets the upper limit for all cores.


Also this.

For the server space TDP == PPT. Same goes for Threadripper.

 

[Abwx]

I don't get the picture.


64 C @ 2.45 on 7nm = 280W.
64 C @ 2.25 on 7nm = 220W.
64 C @ 2.25 on 5nm = 110W
96 cores on 5nm = 165W.
2X for AVX512 = 330W. ( accounting for 100% + for AVX512 and 50% for more cores. 110W>330W)

We have 400W here.

Maybe PCIe 5.0 is the culprit, but these numbers are high.

There s also more RAM channels...

That being said when we account for the I/O using about 80W on Milan that leave about 3W/core, with 96 core this would require almost 300W just for the computing parts.

Also an increased TDP can be a way to improve efficency of the whole system since 96 cores will use 50% more surrounding hardware.

 

[Kedas]

Keywords : 'August 4' , 'unbeatable'

https://twitter.com/x/status/1551599088411545610

You missed key sentence on that page:

Supporting the recent launch of AMD Ryzen™ 7000 Series processors,

So launch before August 4 ????? they really going to have to hurry up.
or someone wrote down the wrong date.

AMD Meet the Experts - An Exclusive Look at Partner Products: A Showcase of The New AM5 Motherboards

explore.amd.com

edit: could be the 'launch' event to say that they will be available in September.

 

[nicalandia]

YuuKi_Ans will have his hands on QS samples of Genoa very soon.

 

[deasd]

You missed key sentence on that page:

So launch before August 4 ????? they really going to have to hurry up.
or someone wrote down the wrong date.

AMD Meet the Experts - An Exclusive Look at Partner Products: A Showcase of The New AM5 Motherboards

explore.amd.com

edit: could be the 'launch' event to say that they will be available in September.

'recent launch' doesn't mean anything, can be earlier than August 4 or later. Last rumored date is after mid-September you can buy one, at earliest, and looks like this event is not a launch of anything, just a showcase of some mobos paired with Raphael.

 

[Kedas]

'recent launch' doesn't mean anything, can be earlier than August 4 or later. Last rumored date is after mid-September you can buy one, at earliest, and looks like this event is not a launch of anything, just a showcase of some mobos paired with Raphael.

recent means not long ago, (on august 4)
But I also think it's more likely it's mid September.
What this webinar is about exactly isn't really relevant, the time reference to a launch is the point

 

[maddie]

recent means not long ago, (on august 4)
But I also think it's more likely it's mid September.
What this webinar is about exactly isn't really relevant, the time reference to a launch is the point

Unless the ability to write has further deteriorated, as we witness daily, referencing a "recent launch" means it has already happened, no interpretation needed here.

You are correct, of course, launch and availability, are different things.

 

[eek2121]

TDP determines base clocks, there's no escaping this. @maddie argues the base clocks from the EPYC 9664 leak don't match the TDP. Why that happens is too speculative for me atm.

Genoa has 50% more cores than Milan (for top end SKUs). This alone will lead to lower base clocks, even on a new process. Depending on AMD's AVX-512 implementation, that may also lead to lower base clocks.

However, I'm not super trusting of these 'leaks' personally, because it seems like a rather large regression.

 

[LightningZ71]

If my understanding of Genoa is correct, we have the following:

The I/O die is now on N6 and uses notably less energy, even with 50% more memory channels, higher operating speeds to support them, in addition to 50% more Ser/Des links.

The CCDs have moved to N5 (with AMD customizations) and consume less power per transistor at the same clock speeds while having modestly more transistors in the core and double the L2.

This leads me to believe that:

For comparable products, say a 64 core Genoa part compared to a 64 core Milan part, there should be notable power headroom for significantly higher clocks all around for Genoa, assuming that thermals are managed.

For different products, say the 96 core Genoa vs. The 64 core Milan, the Genoa may have a slight base clock regression per core when running heavy AVX512 code, but should have roughly comparable clocks to the Milan part on "generic x86 code" but will still have substantially more total throughput due to having more cores and the memory bandwidth to support it.

In most cases, we should expect that Genoa should allow for higher sparse single core boost clocks largely due to the process improvement.

Any of this too far off?