Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[nicalandia]

Typically DDR5 effects would already be included in IPC, since it purely affects the number of instructions you will execute per cycle.

IPC should be isolated from IO/PCI/DDR bottlenecks.

We can see that thanks to Intel extending Skylake for 5 years and we see no difference in IPC from DDR3 and DD4 or even DDR5 in apps like Cinebench, Dolphin emulation. 3D particle movement, WinRAR, HandBreak, POV-Ray, 7-zip

Gaming Performance is not indicative IPC performance

 

[itsmydamnation]

IPC should be isolated from IO/PCI/DDR bottlenecks.

We can see that thanks to Intel extending Skylake for 5 years and we see no difference in IPC from DDR3 and DD4 or even DDR5 in apps like Cinebench, Dolphin emulation. 3D particle movement, WinRAR, HandBreak, POV-Ray, 7-zip

Gaming Performance is not indicative IPC performance

thats a really bad take.

So now better prefetchers and predictors that do sweet FA for something like Cinebench but heaps for "Games" are not IPC performance ( WTF that is....)

heaps of the things you just mentioned are L1 , L2 benchmarks , i wonder why memory didnt have an effect on performance.....

IPC is IPC and is determined by complete end to end architecture per target workload.

 

[eek2121]

5950X boosted past 5 Ghz on day one release. B2 stepping are boosting to 5.1 or more. Zen4 is going to surprise many people

B2 didn't really give any frequency or power consumption improvements. There was a rumor claiming otherwise, but it was proved to be bunk.

AMD shocked me with the single-core boost jump from Zen2 -> Zen3. Same process, but 400+ MHz jump? That was unexpected. Kinda why I have muted expectations for Zen4.

Let's put this another way. A 5800X or 5950x on the N5P process at the same frequencies would have at most an 85W PPT (vs 142W now, also assuming no other design challenges/bottlenecks exist).

AMD is using some custom variant of N5 (probably N5P with tweaked libraries), they are claiming much greater improvement than the figure I just mentioned in the only marketing slide released.

I would be really surprised if we did not see a massive overall uplift, much greater than what people here are mentioning. I'm thinking specifically in terms of multicore performance. 20-30% sounds spot on for single core performance depending on workload. I guess we will find out, possibly as soon as a month from now (I've always believed the unveiling would be at Computex).

 

[deasd]

Things are coming faster than expected? CPU-Z now can recognize Raphael APU(list Rembrandt & Raphael together)

CPU-Z | Softwares | CPUID

CPU-Z for Windows® x86/x64 is a freeware that gathers information on some of the main devices of your system : Processor name and number, codename, process, package, cache levels. Mainboard and chipset. Memory type, size, timings, and module specifications (SPD). Real time...

www.cpuid.com

CPU-Z 2.01 April 13th, 2022

AMD Rembrandt & Raphael APUs (RDNA2).

 

[randomhero]

Things are coming faster than expected? CPU-Z now can recognize Raphael APU(list Rembrandt & Raphael together)

CPU-Z | Softwares | CPUID

CPU-Z for Windows® x86/x64 is a freeware that gathers information on some of the main devices of your system : Processor name and number, codename, process, package, cache levels. Mainboard and chipset. Memory type, size, timings, and module specifications (SPD). Real time...

www.cpuid.com

We discussed this few pages ago. There is greymon55's twitt about zen4 starting mass production. This confirms that rumour somewhat.
Basically, Zen4 is at packaging facilities already.
I am expecting Computex preview/pre-launch and August release.

 

[Mopetar]

IPC should be isolated from IO/PCI/DDR bottlenecks.

Memory is always going to be somewhat of a bottleneck, even for workloads where most of the data can fit in cache.

In some cases the number of cache misses results in an IPC well below 50% of the theoretical maximum. As a CPU gets more powerful it means that it needs even faster memory access to be able to keep all of the execution units fed.

Look how much Alder Lake benefits from DDR5 in the benchmarks that have both types of memory tested.

 

[nicalandia]

Memory is always going to be somewhat of a bottleneck, even for workloads where most of the data can fit in cache.

In some cases the number of cache misses results in an IPC well below 50% of the theoretical maximum. As a CPU gets more powerful it means that it needs even faster memory access to be able to keep all of the execution units fed.

Look how much Alder Lake benefits from DDR5 in the benchmarks that have both types of memory tested.

In Skylake it did not make any difference (Weather it was a 6700K or 10900K) in many apps. I am also seeing no difference between Ze3 with DDR4 and Zen3+ with DDR5

DDR4 vs. DDR5 on Intel Core i9-12900K Alder Lake Review

The Intel Alder Lake platform has support for both DDR5 and DDR4 memory. We ran 38 application benchmarks and 10 games at multiple DDR4 configurations to learn what performance to expect when using DDR4 vs. DDR5 on 12th Gen, and whether there's a point at which DDR4 performance can beat the much...

www.techpowerup.com

Should IPC really be measured by the Memory Subsystem instead of the actual CPU design?

 

[igor_kavinski]

I am also seeing no difference between Ze3 with DDR4 and Zen3+ with DDR5

Has anyone done that comparison?

 

[biostud]

In Skylake it did not make any difference (Weather it was a 6700K or 10900K) in many apps. I am also seeing no difference between Ze3 with DDR4 and Zen3+ with DDR5

DDR4 vs. DDR5 on Intel Core i9-12900K Alder Lake Review

The Intel Alder Lake platform has support for both DDR5 and DDR4 memory. We ran 38 application benchmarks and 10 games at multiple DDR4 configurations to learn what performance to expect when using DDR4 vs. DDR5 on 12th Gen, and whether there's a point at which DDR4 performance can beat the much...

www.techpowerup.com

Should IPC really be measured by the Memory Subsystem instead of the actual CPU design?

Isn't the memory controller part of the CPU design, so the IPC is a partly dependent on how fast the CPU can fetch data from RAM?

 

[nicalandia]

Isn't the memory controller part of the CPU design?

No, Zen 3 was designed to be IO Agnostic. EPYC uses 14nm IO, Matisse uses 12nm and Cessane used 7nm and now Rembrandt now uses 6nm. This should have no barring on the performance of Apps that tests IPC for example SPEC2006/2017

 

[igor_kavinski]

So basically IPC testing involves only applications that can fit their entire data set in the caches. They pull the data from RAM at the start and then don't touch RAM during the entirety of their execution. That's very few practical applications.

 

[Mopetar]

In Skylake it did not make any difference (Weather it was a 6700K or 10900K) in many apps. I am also seeing no difference between Ze3 with DDR4 and Zen3+ with DDR5

DDR4 vs. DDR5 on Intel Core i9-12900K Alder Lake Review

The Intel Alder Lake platform has support for both DDR5 and DDR4 memory. We ran 38 application benchmarks and 10 games at multiple DDR4 configurations to learn what performance to expect when using DDR4 vs. DDR5 on 12th Gen, and whether there's a point at which DDR4 performance can beat the much...

www.techpowerup.com

Should IPC really be measured by the Memory Subsystem instead of the actual CPU design?

A CPU without a memory subsystem is worthless. Even if you don't think it's important, neither AMD or Intel will design something that's just going to hit a wall when it comes to being constrained by memory.

If you don't want to consider the memory subsystem it's not too difficult to determine what the theoretical peak IPC is if you have enough details about the architecture of the core.

Just because you can find one benchmark that doesn't have a memory bottleneck doesn't mean that it's indicative of all applications. There are plenty where it's important and it's not just in gaming:

There's two where it's a 30% improvement. That's quite significant.

 

[Panino Manino]

One time we had a consumer motherboard and CPU with 3 channel memory.
What's preventing desktops from overcoming 2 channel? Isn't there for this market to upgrade to more channels?

 

[gdansk]

One time we had a consumer motherboard and CPU with 3 channel memory.
What's preventing desktops from overcoming 2 channel? Isn't there for this market to upgrade to more channels?

Wasn't it basically the HEDT of the day? HEDT has 4/6/8 channel instead these days.

 

[Markfw]

One time we had a consumer motherboard and CPU with 3 channel memory.
What's preventing desktops from overcoming 2 channel? Isn't there for this market to upgrade to more channels?

My 1950x is 4 channel. What is your point ?

A $300 motherboard with a $400 CPU (todays prices) is desktop. Not an expensive CPU.

 

[Panino Manino]

My 1950x is 4 channel. What is your point ?

A $300 motherboard with a $400 CPU (todays prices) is desktop. Not an expensive CPU.

Threadripper.
I'm talking "normal people's desktops", "just" Ryzens.
Also, I said "3 channels", not 4. Just an extra channel would already satisfy me and isn't this step forward becoming necessary? Number of cores is increasing faster than RAM speeds. Many common CPUs today benefits greatly from faster (and more expensive) memory sticks.

There's some technical limitation that makes it more difficult to make a CPU/Mobo with 3 channels instead of 4 channels?

 

[deasd]

Pretty high Vcore..... could it being translate to high stock clock?

https://twitter.com/x/status/1514620039789363201

 

[maddie]

Threadripper.
I'm talking "normal people's desktops", "just" Ryzens.
Also, I said "3 channels", not 4. Just an extra channel would already satisfy me and isn't this step forward becoming necessary? Number of cores is increasing faster than RAM speeds. Many common CPUs today benefits greatly from faster (and more expensive) memory sticks.

There's some technical limitation that makes it more difficult to make a CPU/Mobo with 3 channels instead of 4 channels?

Just cost. Think of what this could do to APUs.

 

[soresu]

Pretty high Vcore..... could it being translate to high stock clock?

https://twitter.com/x/status/1514620039789363201

View attachment 60070

Interesting.

The img implies it is B650 chipset, so we're getting budget boards at the same time at least unlike with x570 and the wait for B550.

 

[RnR_au]

Interesting.

The img implies it is B650 chipset, so we're getting budget boards at the same time at least unlike with x570 and the wait for B550.

PCIe5 with X670 maybe?

 

[soresu]

PCIe5 with X670 maybe?

A rumour puts X670 as basically 2xB650 rather than what X570 is as basically the IOD for Zen2/3 AM4 - so I could see it turning up in BIOS readings similar in early revisions before full branding.

 

[A///]

We discussed this few pages ago. There is greymon55's twitt about zen4 starting mass production. This confirms that rumour somewhat.
Basically, Zen4 is at packaging facilities already.
I am expecting Computex preview/pre-launch and August release.

Allow me to place my tinfoil hat on and profess my fortune telling abilities, my fine gentleman. I suspect you may be right but it may also be a July launch. I only say that while it may not fit the perceived timelines leaked a half year ago because of how AMD loves to play with their product name numbers and dates.

Though at this moment I can't remember why Zen 2 came out in July 2019.

 

[DisEnchantment]

Pretty high Vcore..... could it being translate to high stock clock?

https://twitter.com/x/status/1514620039789363201

View attachment 60070

Zen 3 Vcore is much lesser than that. Very strange to have such high Vcore considering part of N5 efficiency is improving operation at lower voltages.
According to TSMC, N4X is officially their only leading edge node that is designed to operate beyond 1.2V.

It is possible they replaced the LDO with an IVR which could explain such high Vcores.
They would need to do that at some point, because lowering voltage means they need to drive up current to maintain switching performance.
This has the effect of reducing VDD pads because higher voltage is delivered in fewer pads and supply is kept very close to the logic resulting in lower I2R losses.

Zen 2 and above have 4 LDOs on both sides of the L3 which take around 3-4 mm2 of area.
But using N5 real estate to make an IVR is too wasteful ... unless there is really a fanout layer underneath the die where they can use RDLs to weave the needed inductors.
Nevertheless very interesting if true.

 

[A///]

Double posting because I have a small migraine going on. Zen 4 of what I know and what most know is that it will have higher clocks based on what we saw during the ces 2022 presentation and there was a recent loose lipped statement of Zen 4/am5 memory overclocking to be big. Whatever the heck that means.

From the engineering sample video at CES the gaming performance looks to be top stuff but again it was some build of Halo and I'm not entirely sure if Halo is a valid measure of performance.

 

[randomhero]

Zen 3 Vcore is much lesser than that. Very strange to have such high Vcore considering part of N5 efficiency is improving operation at lower voltages.
According to TSMC, N4X is officially their only leading edge node that is designed to operate beyond 1.2V.

It is possible they replaced the LDO with an IVR which could explain such high Vcores.
They would need to do that at some point, because lowering voltage means they need to drive up current to maintain switching performance.
This has the effect of reducing VDD pads because higher voltage is delivered in fewer pads and supply is kept very close to the logic resulting in lower I2R losses.

Zen 2 and above have 4 LDOs on both sides of the L3 which take around 3-4 mm2 of area.
But using N5 real estate to make an IVR is too wasteful ... unless there is really a fanout layer underneath the die where they can use RDLs to weave the needed inductors.
Nevertheless very interesting if true.

Someone please correct me, but Zen3 has quite high voltage in single core boost. Could be just reading single core boost voltage?

Although, your speculation has some legs.