Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[NTMBK]

No DDR3 or DDR2 or DDR support either…

But what about my RDRAM kit?!

 

[LightningZ71]

Hey, you skipped my PC-133 dram!

 

[itsmydamnation]

Hey, you skipped my PC-133 dram!

a7n8x owners represent!

 

[Ajay]

Hey, you skipped my PC-133 dram!

I want my, I want my EDO

 

[DrMrLordX]

I want my, I want my EDO

FPM RAM not good enough for you?

 

[LightningZ71]

Keep your hands off of my SIMMS!

 

[DrMrLordX]

Keep your hands off of my SIMMS!

Imagine Zen4 with a 33 MHz bus. lol. Better stick with the DDR5.

 

[eek2121]

Nobody credible ever said anything else though?

About Zen 4 supporting EDO RAM, DDR, DDR2, DDR3, RDR, etc? of course not!

 

[Saylick]

Imagine Zen4 with a 33 MHz bus. lol. Better stick with the DDR5.

LOL, I bet even 8-layers of V-cache per CCD wouldn't be enough to make that work.

 

[scannall]

About Zen 4 supporting EDO RAM, DDR, DDR2, DDR3, RDR, etc? of course not!

What? No Centronics support? No SCSI? No RS 232. Barbarians I tell yeah. And no floppies? OMG!

 

[Ajay]

FPM RAM not good enough for you?

Obviously not! Man, the money I've spent on RAM over the years.

 

[soresu]

LOL, I bet even 8-layers of V-cache per CCD wouldn't be enough to make that work.

If the V cache was something denser than SRAM maybe.

Come on bois at AMD/Intel/nVidia, we wanna see some MRAM cache action!

 

[IntelUser2000]

If the V cache was something denser than SRAM maybe.

Come on bois at AMD/Intel/nVidia, we wanna see some MRAM cache action!

What about their eDRAM on the Intel 4 process??

128MB on 22nm
256MB on 14nm
512MB on 10nm
1GB on Intel 4

8GB 8 layers.

 

[soresu]

What about their eDRAM on the Intel 4 process??

128MB on 22nm
256MB on 14nm
512MB on 10nm
1GB on Intel 4

8GB 8 layers.

I'd rather see volatile memory die a death sooner than later.

I'm hoping that the proposed capacitorless DRAM devices to continue DRAM scaling past 1x nm will quickly be superseded by advanced MRAM - either would allow scaling to continue, but MRAM has greater switching speed and efficiency potential, and MRAM potentially has full non volatility allowing for persistance and zero refreshes in idle state.

 

[lobz]

Is it really all about the power requirements? I guess the power delivery quality and quantity surely have a role in that but still.

Zen 2/3 don't really easily raise clock even with high voltage compared to Intel's classic. Is 5nm alone gonna change this?

Why 5nm alone? It is also a new uarch

 

[lobz]

What? No Centronics support? No SCSI? No RS 232. Barbarians I tell yeah. And no floppies? OMG!

i always liked scsi

 

[Mopetar]

LOL, I bet even 8-layers of V-cache per CCD wouldn't be enough to make that work.

For some systems it might be okay. Using the current 64 MB layers, that would be a total of 512 MB of RAM, which is paltry today, but was quite a lot back in the day. If you did have an environment that could comfortably fit in that space, it would essentially cut memory access time in half, though in reality the latency for the L3 cache would likely increase.

 

[Kedas]

Do you think it's possible that the only physical difference between Zen4c and Zen4 is the memory: L2 , L3, V-Cache?

 

[DisEnchantment]

Do you think it's possible that the only physical difference between Zen4c and Zen4 is the memory: L2 , L3, V-Cache?

I don't think it would just those, just an early thought since we don't have details yet.

• Zen4c would likely not use the same process as the HPC optimized Zen4. Very likely lower power and density optimized flavor of N5, just like N7 for mobile 5000 series.
  • E.g. Cezanne has 62.5 MTr/mm2 density compared to 51.5 MTr/mm2 for Zen3 CCD even though Cezanne has a lot more IO blocks. If we remove the IO blocks, Cezanne could probably be 70+ MTr/mm2 (Apple got 82 MTr/mm2 on N7 for example)
• L3 will get a cut like mobile series to 2MB/slice
• L2 will likely stay the same as normal Zen 4 at 1MB. Doubling the L2 of Zen 4 (i.e. 2MB) would make it 2x the size of L3 slice, in other words, 2MB L2 has similar size as 4 MB L3 slice.
• V-Cache likely not, because they cut the L3 to begin with, why add again, plus they need room to add the LDOs and the TSVs. Zen3 has LDOs between the L3 gaps to power the V Cache.

25-30% density gain from using Mobile variant of process + 20% reduction in area by cutting L3 in half + Cutting TSV area 2-3 mm2 + reducing LDO area.
That might just be enough to fit 2 such CCX in Zen4c.

 

[MadRat]

i always liked scsi

There's no modern pain like Microchannel.

 

[MadRat]

Is Zen 4 to Zen 4c what iPhone 4 was to iPhone 4c?

Interesting times.

 

[Joe NYC]

But I'm not sure this is really a positive for AMD which over the long run should be more interested in a customer base boarder than this. Microsoft's commitment must be significant.

Yeah, that is my working hypothesis as well. Commitment significant enough to essentially cancel the desktop Zen3D to secure this commitment.

Given that Milan (and Milan-X, once it becomes available to other customers in addition to MSFT) is in extremely tight supply, what could this commitment be, if AMD is already able to sell all they are making and then some?

 

[LightningZ71]

i always liked scsi

Look at you and your nodern interface standards! Why would you skip over my favorite RLL and MFM interfaces?!?! I'm going to have to whip out my Hayes 300 baud modem and trash talk you on my local BBS. Now where dud I put my old rotary phone and acoustic cradle for my handset. I just hope I can still load the program off my cassette tape in that bulky player...

 

[Joe NYC]

It would certainly make sense in cooler climates to use that energy for heating in the winter, if you have a way to get it there (i.e. steam tunnels or the like) If you could site a datacenter near something that needs huge quantities of hot water (imagine the world's biggest laundromat) that would be perfect.

There are evolving technologies that promise to do a better job of making use of waste heat. It remains to be whether it can do significantly better than the Peltier effect which isn't efficient enough to bother with energy recovery from waste heat in datacenters or industrial processes that produce a lot of waste heat like cement plants or oil refineries.

In urban areas (such as NYC) there are power plants that sell waste heat to residences as steam. But the steam leaving these power plants must be a lot higher temperature than what a datacenter can produce.

 

[Thibsie]

I say, nothing beats AppleTalk.