Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[moinmoin]

SPR w/ HBM will have 14 EMIB connections. On first chiplet attempt. Kudos to Intel.

While the ability is applaudable, I'm personally not sure Intel really deserves kudos for their approach. Especially PVC appears to be overenginered, SPR doesn't strike me as particularly elegant either.

 

[Saylick]

While the ability is applaudable, I'm personally not sure Intel really deserves kudos for their approach. Especially PVC appears to be overenginered, SPR doesn't strike me as particularly elegant either.

Yep, laudable on paper, but if the comparison table between FOEB vs. EMIB is true (i.e. 80-90% yield for EMIB), 14 EMIB connections is going to really bring down overall yields of PVC. Not sure if this is how EMIB cumulative yields will work but 0.9^14 is 0.23... That doesn't look promising at all. It almost feels like Intel's 10nm woes all over again: overengineered, too aggressive, delayed.

 

[DisEnchantment]

Yep, laudable on paper, but if the comparison table between FOEB vs. EMIB is true (i.e. 80-90% yield for EMIB), 14 EMIB connections is going to really bring down overall yields of PVC. Not sure if this is how EMIB cumulative yields will work but 0.9^14 is 0.23... That doesn't look promising at all. It almost feels like Intel's 10nm woes all over again: overengineered, too aggressive, delayed.

Let's see. Important is that the two x86 vendors are trying to one up each other. Innovations will be plenty on both sides.
I am glad ADL with all its warts and moles is not a damp squib.

Let's see AMD's hand next.

 

[tomatosummit]

Yep, laudable on paper, but if the comparison table between FOEB vs. EMIB is true (i.e. 80-90% yield for EMIB), 14 EMIB connections is going to really bring down overall yields of PVC. Not sure if this is how EMIB cumulative yields will work but 0.9^14 is 0.23... That doesn't look promising at all. It almost feels like Intel's 10nm woes all over again: overengineered, too aggressive, delayed.

What's the source on that yield thing? I remember charlie's claims but we're probably on the third generation of emib now (kabyG and their cancelled internal XE gpu) and I expect it to be good enough for mass market now. Especially if it's being sprinkled like confetti on the spr and pv packages which are going to be intel's biggest market and biggest growth market respectively.

 

[Saylick]

What's the source on that yield thing? I remember charlie's claims but we're probably on the third generation of emib now (kabyG and their cancelled internal XE gpu) and I expect it to be good enough for mass market now. Especially if it's being sprinkled like confetti on the spr and pv packages which are going to be intel's biggest market and biggest growth market respectively.

Source: https://www.3dincites.com/2020/07/iftle-456-spil-fan-out-embedded-bridge-foeb-technology/

There's probably some bias in that table since it comes from a competitor to Intel's EMIB, but even giving Intel the benefit of the doubt and assuming the yields are actually 95%, 0.95^14 is still <50%. Not good, not terrible.

 

[maddie]

Source: https://www.3dincites.com/2020/07/iftle-456-spil-fan-out-embedded-bridge-foeb-technology/

There's probably some bias in that table since it comes from a competitor to Intel's EMIB, but even giving Intel the benefit of the doubt and assuming the yields are actually 95%, 0.95^14 is still <50%. Not good, not terrible.

It seems some of the failures are embedding the bridges themselves in the substrate. So not quite as bad as it appears.

 

[DisEnchantment]

Another slide from Hyperion Research, El Capitan full system delivery in late 2022. This system uses variant of Zen4 with MI300. I think there is a chance the El Capitan will be upgraded.

 

[Ajay]

In other news ... Zen4 DIY postponed. Hopefully not :|

I hit up a couple of the usual leak sites and didn't see this. Twitter leaker?

 

[moinmoin]

I think there is a chance the El Capitan will be upgraded.

Is that your interpretation of "Full system delivery in late 2022, with full production, late 2023"? Seems like an odd sentence, especially with that random comma placement in there. I feel "full system" may refer to all the racks and infrastructure, with all the 9000+ node sleds coming in bit by bit until late 2023 for "full production". Considering LLNL already has a preview running with RZNevada (based on Epyc Zen 2 Rome + CDNA1 MI100) I can't really imagine them doing yet another intermediary step.

 

[DisEnchantment]

Is that your interpretation of "Full system delivery in late 2022, with full production, late 2023"? Seems like an odd sentence, especially with that random comma placement in there. I feel "full system" may refer to all the racks and infrastructure, with all the 9000+ node sleds coming in bit by bit until late 2023 for "full production". Considering LLNL already has a preview running with RZNevada (based on Epyc Zen 2 Rome + CDNA1 MI100) I can't really imagine them doing yet another intermediary step

I think the US DOE will upgrade the system specs >2EF based on what some Govt HPC researchers are discussing on twitter because of recent disclosures of that China has multiple Exascale machines.
Nothing more, just my interpretation of the conversation.

 

[uzzi38]

I hit up a couple of the usual leak sites and didn't see this. Twitter leaker?

There was a couple of articles saying November.

But afaik Genoa starts shipping to select customers in H1. I highly doubt desktop Zen 4 comes 5 full months later.

 

[Ajay]

I think the US DOE will upgrade the system specs >2EF based on what some Govt HPC researchers are discussing on twitter because of recent disclosures of that China has multiple Exascale machines.
Nothing more, just my interpretation of the conversation.

China is spending money like there is no tomorrow, especially on defense related projects. In the past many supercomputers went to 'scientific institutes' that were actually fronts for military research. I assume they are also using HPC's for other 'typical' scientific research targets.

 

[DisEnchantment]

I hit up a couple of the usual leak sites and didn't see this. Twitter leaker?

My Poor attempt at humor.
Zen4 is getting booked in major quantities regularly before it even launches.
First El Capitan, then GENCI, then the previous known win

Microsoft brings Azure supercomputing to UK Met Office | Microsoft Azure Blog

The UK Meteorological Office (Met Office) is working with Microsoft to deliver advanced supercomputing capabilities for weather and climate research, ensuring the continuation of the Met Office’s international leadership in this area.

azure.microsoft.com

Each quadrant will consist of an HPE Cray EX supercomputer integrated into Azure, initially using 3rd generation AMD EPYC processors, which will later be augmented with next generation AMD EPYC processors. The first generation of the supercomputer solution will have a combined total of over 1.5 million processor cores

Then the likes of Azure claiming priority. Will be a sliver trickling down to DIY if you ask me.
But end 2022 is when a lot of new capacity will be coming online. So remains to be seen.

 

[xilli_fiberbit]

There is too a China exascale system which could move from Hygon CPU to ZEN4, planned in 2022 but delayed to make the switch :

https://twitter.com/x/status/1460269583240085509

 

[moinmoin]

For that matter AMD's share of the Top500 is growing fast:

https://twitter.com/x/status/1460334823000756226

 

[Ajay]

Then the likes of Azure claiming priority. Will be a sliver trickling down to DIY if you ask me.
But end 2022 is when a lot of new capacity will be coming online. So remains to be seen.

I can see Raphael coming out with the same limited supply problem as the Ryzen 5000 series processors. I'm sure scalpers are tuning up their buying bots as we speak . People who really want to upgrade immediately will probably need to pre-order.

 

[Saylick]

Is it sad to report that the last time I built a full-blown desktop was almost 10 years ago? But that was mostly because I was a poor college student to even try to upgrade more frequently. I have a decent job now, but unfortunately the current state of the DIY market ain't making it easy or financially wise for me to get back into the "game", so to speak. Short supply, scalpers, raised prices, etc. aren't conducive at all to regular Joes like myself who want a $1000 PC and get something decent out of that budget. I still keep up with all of the rumors and news because this is an exciting time with respect to hardware, but it sucks seeing the hobby become more and more exclusive over time.

 

[jamescox]

You're not wrong but I think people are just underestimating the margins on desktop cpus, especially with zen3 parts.
compare the zen2 desktop cpus where the 3300 was $130 and 3600 was easily available for ~$160 to the cheapest 5600x which still is $300. Almost the same BOM for them but over twice the cost of the cheapest parts. We know from amd's own reveals and slides that a dual ccd cpus are only 60% more expensive to manufacture but are selling for more than double the cost on the cheapest parts again.
The 5000x ryzens have extreme margins no matter how you look at it.

On the otherhand a distributer (dell/hp) for server cpus is going to be purchasing from amd in much higher volumes and consistently as well. AMD can afford to reduce margins there and aren't dell's asking prices above the rrp anyway so their discounts aren't as kind as they seem.
This is again coupled with the large increases to asking price for epyc cpus as each zen generation launched. MilanX is going to be eye watering.

I am aware I've missed out various things like distribution and support that will chew through margins.

You seem to be comparing volume purchase price with retail price of desktop parts. Resellers and OEMs don’t pay retail prices for desktop processors either. I have no idea what volume pricing for desktop processors actually is. Intel tends to quote 1000 unit tray price, but I don’t think AMD does that.

 

[jamescox]

Every 32/48/64 core epyc we buy has full l3 cache , ie 8ccds , the uncore is also way bigger.

A good 4 X in manufacturing costs then a 2 ccd ryzen part.

I doubt that is actually true, although yields on the IO die are probably really good. The package is much larger and likely has more layers to accomplish the routing. That would be proportionately more expensive. When you get to monolithic die, 4x the size is a lot more than 4x the cost due to yields. It is a lot closer to 4x the cost using An MCM compared to a monolithic die, but it will still be quite a bit more expensive. I have wondered if we will actually see Zen 4 based Threadripper with how expensive SP5 will be.

 

[jamescox]

SPR w/ HBM will have 14 EMIB connections. On first chiplet attempt. Kudos to Intel.
Remains to be seen what AMD has in store in this regard.

In other news ... Zen4 DIY postponed. Hopefully not :|

Hewlett Packard Enterprise Builds New Supercomputer for France’s GENCI-CINES to Advance Nation’s Open Science and R&D

Hewlett Packard Enterprise (NYSE: HPE) today announced that it is building one of Europe’s most powerful supercomputers to be installed and operated a

www.businesswire.com

• Powerful compute and accelerated compute to improve modeling, simulations and data and image-intensive workflows using optimized 3rd Gen AMD EPYC™ processors combined with AMD Instinct™ MI250X accelerators in one partition, and next generation AMD EPYC processors, codenamed “Genoa” in the second partition.

Trento + Genoa

Almost everything has been delayed with the covid and supply chain issues. Intel has become more of “I will believe it when I see it” than AMD at this point. I don’t have much confidence in Intel managing to execute on this. I am also actually wondering how well it will compete against massive SRAM cache parts from AMD. The massive caches can hide the lower bandwidth of the memory system in many cases. Also, HBM is high bandwidth, but it is not low latency. It still has DRAM-like latency. We may see some benchmarks dominated by AMD and some by intel if competing products are actually available in the market at the same time. For may applications, it will be better to use a CPU plus GPU than just a CPU with HBM. Systems with Epyc and cDNA compute with unified memory might come out the best on many applications.

 

[moinmoin]

Almost everything has been delayed with the covid and supply chain issues. Intel has become more of “I will believe it when I see it” than AMD at this point.

Intel even had all these issues way before covid added to the mess.

 

[Manabu]

Nobody is speculating on the quantity of L1 cache for Zen4c/D? It will be optimized for a lower peak clock speed and according to AMD will have a new cache hierarchy. I doubt that refers only L2 and L3 cache. If they will fiddle with removing FP compute power, they can also fiddle adding extra L1 cache keeping the the same latency in cycles. The end result might be similar to Apple's big cores cache hierarchy.

 

[Ajay]

Nobody is speculating on the quantity of L1 cache for Zen4c/D? It will be optimized for a lower peak clock speed and according to AMD will have a new cache hierarchy. I doubt that refers only L2 and L3 cache. If they will fiddle with removing FP compute power, they can also fiddle adding extra L1 cache keeping the the same latency in cycles. The end result might be similar to Apple's big cores cache hierarchy.

Did AMD mention using an SLC?

 

[Mopetar]

Every 32/48/64 core epyc we buy has full l3 cache , ie 8ccds , the uncore is also way bigger.

A good 4 X in manufacturing costs then a 2 ccd ryzen part.

Cheapest 32-core Epyc with 8 chiplets has a list price of $2730. AMD doesn't use any 4-core chiplets for consumer parts so we can just ignore these. Even if they did, they'd have to charge a lot more than anyone would pay for those to make more money than in the server market.

The 8x 6-core configuration lists for $5000. AMD sells the desktop parts for $300/$550. Ignoring any differences is costs for production, you'd need to be getting a 50% discount just to make it comparable. The cheapest 8x 8-core Epyc is also only $5000, so the numbers work out better for you there since the desktop parts are $450/$800 and you'd only need ~30% discount if we're comparing against the 5800X, which is generous since that didn't see nearly as much popularity with consumers as the other chips.

Maybe your company does get a discount on the hardware good enough to cover that difference, but I'd also have to ask if there's a support contract bundled with that which brings the actual cost back in line with the list prices.

 

[moinmoin]

Nobody is speculating on the quantity of L1 cache for Zen4c/D?

The whole Zen family so far hasn't seen a change in its L1$ quantity of 64KiB. Only change so far was how its use is partitioned in Zen 2. So far we heard Zen 4 will increase L2$. But a L1$ change is more delicate so I'd deem it very unlikely an optimization step like Zen 4c will contain a big change there.