Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 5000)

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What do you expect with Zen 4?


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    145

DisEnchantment

Senior member
Mar 3, 2017
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Page 39 (45 in the PDF) agrees with scannall, "Purchase obligations" is 1,677 mil this year, 592 mil next year, and after that there's only 21 mil left that could well be mostly unrelated to the WSA.
Looks like Zen2 products will be the last ones to use the GF IODs because if Zen3 is still using parts from GF the number for next year should still be considerably higher than this year.
 

Gideon

Senior member
Nov 27, 2007
833
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Looks like Zen2 products will be the last ones to use the GF IODs because if Zen3 is still using parts from GF the number for next year should still be considerably higher than this year.
Nice findl! Considering AMD just released some Zen 1 Embedded parts in November and is also still producing at least some other zen+ parts (at least 1600AF + legacy Threadrippers), not to mention some server customers will still be buying Rome even a while after Milan is out it seems indeed extremely unlikely now that Zen 3 is using Globalfoundries I/O die. Those numbers would be totally in another league in that case.
 

Tuna-Fish

Golden Member
Mar 4, 2011
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Looks like Zen2 products will be the last ones to use the GF IODs because if Zen3 is still using parts from GF the number for next year should still be considerably higher than this year.
That's not the amount they are spending or intending to spend, it's the amount they are obligated to spend because of the WSA. If they want to, they can purchase more stuff from them, but from next year on they can freely choose who they are purchasing things from.
 

DisEnchantment

Senior member
Mar 3, 2017
578
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That's not the amount they are spending or intending to spend, it's the amount they are obligated to spend because of the WSA. If they want to, they can purchase more stuff from them, but from next year on they can freely choose who they are purchasing things from.
You are right... but they are only obligated to spend/or pay a certain amount only if they manufacture something on a process larger than 7nm.

1586362540793.png
 

moinmoin

Golden Member
Jun 1, 2017
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You are right... but they are only obligated to spend/or pay a certain amount only if they manufacture something on a process larger than 7nm.

View attachment 19329
That's not how I'm reading it. The amount they have to spend is essentially fixed, they can't reduce it by moving to 7nm and lower faster. And they can't move CPUs (plus some of the GPUs) larger than 7nm away from GloFo, all the AMD dies at GloFo with 5 or even 10 years of guaranteed availability will stay at GloFo.
 

Ajay

Diamond Member
Jan 8, 2001
7,064
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Well, @uzzi38 posted an update in another thread about TSMC 5nm: https://forums.anandtech.com/threads/speculation-ryzen-4000-series-zen-3.2567589/page-97#post-40132361

I'm quoting here for simplicity sake (translation from Chainnews)
Huawei cut TSMC 5nm orders due to lower smartphone demand. Apple absorbs, asked for 10K more wafers in 4Q, competing with AMD, etc. for "enhanced 5nm" capacity. Reportedly, TSMC developed "enhanced 5nm" process specifically for AMD. AMD requires no less than 20K 12" wpm. Huawei also cut 7nm orders.

But Nvidia, AMD and other big customers simultaneously increased 7nm orders. Not only is TSMC's 5nm production capacity fully turned on starting from 2Q, 7nm capacity will also continue to be fully utilized until the end of the year.
Looks like very good news for Genoa!
 
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RetroZombie

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Nov 5, 2019
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Looks like very good news for Genoa!
It's from tsmc best interests force amd to be the first to adopt a new node before everyone else.
Because thanks to it's chiplet architecture even at a very bad yield, let's assume 40% of the chip is good, they can cut it down and put two of those bad yield chiplets and actually create a high end product, that is profitable.

If you ask nvidia, apple or anyone else and cut 60% of the chip off you get a very low end product, expensive to make and near zero profits.

So amd is a great node pipe cleaner and flaw defect detector to clean node imperfections and early shortcomings.
 

Ajay

Diamond Member
Jan 8, 2001
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It's from tsmc best interests force amd to be the first to adopt a new node before everyone else.
Because thanks to it's chiplet architecture even at a very bad yield, let's assume 40% of the chip is good, they can cut it down and put two of those bad yield chiplets and actually create a high end product, that is profitable.

If you ask nvidia, apple or anyone else and cut 60% of the chip off you get a very low end product, expensive to make and near zero profits.

So amd is a great node pipe cleaner and flaw defect detector to clean node imperfections and early shortcomings.
Apple is the only company I’m aware of that will buy large quantities of risk wafers to begin building up inventory. They are willing to effectively pay more because of lower yields at that point. I doubt AMD would be happy to fill that role given their significantly lower financial strength.
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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I don't think yields are bad in regards to 5nm. It is technically 2nd Gen EUV;

With 7nm+ from Kirin 990 5G and 6nm with Tiger T7520 being 1st Gen EUV. // Effectively making 7nm+/6nm, the 20nm to 16nm or 10nm to 7nm node, relative to 5nm.

20nm/10nm/7nm+ might be bad but 16nm/7nm/5nm will be good because TSMC did those nodes. Which is why 5nm sooner than later will be a better strategy. Especially, with Fab 15 mostly being funneled for 7nm or 6nm and reduced 7nm+ focus. With a "majority amount" of customers doing 7nm(Fab15) -> 6nm(Fab15) and skipping 7nm+(Fab15) for 5nm(Fab18).
 
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RetroZombie

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Nov 5, 2019
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I doubt AMD would be happy to fill that role given their significantly lower financial strength.
Yes you are right that's why i wrote force amd.

Let's explain this first with conversation and videos, than i will explain it latter with chips :)

tsmc: We want zen 5 at our 3nm process as soon as possible.
amd: But the design is not ready. Uah! Uah!
tsmc: No zen5 for you! Come back one year!
amd: Por favor
tsmc: Por favor? Adios muchacho
amd: But i don't get any?
tsmc: 2 million dollars!
amd: What not free?
tsmc: 3 millions dollars extra!
amd: What?
tsmc: No zen5 for you!
amd: Going to kiss samsung!
tsmc: What kissing in my line!
tsmc: No zen5 for you!
samsung: Let's go amd.
amd: Do i know you samsung?!
 
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maddie

Diamond Member
Jul 18, 2010
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Yes you are right that's why i wrote force amd.

Let's explain this first with conversation and videos, than i will explain it latter with chips :)

tsmc: We want zen 5 at our 3nm process as soon as possible.
amd: But the design is not ready.
tsmc: No zen5 for you! Come back one year!
amd: Por favor
tsmc: Por favor? Adios muchacho
amd: But i don't get any?
tsmc: 2 million dollars!
amd: What no longer free?
tsmc: 3 millions dollars extra!
amd: What?
tsmc: No zen5 for you!
amd: Going to kiss samsung!
tsmc: What kissing in my line!
tsmc: No zen5 for you!
samsung: Let's go amd.
amd: Do i know you samsung?!
Shucks, No cartoons?
 

RetroZombie

Senior member
Nov 5, 2019
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The zen2 die:

CPU cores #: 8
L3 cache: 32MB
Size: 100% die

Lets hypothetically assume that the tsmc 7nm would have a very bad yield:
1587292723356.png
CPU cores #: 4
L3 cache: 8MB
Size: 40% good / 60% disabled

Put this on three chiplet packaged and we would be seeing one R7 3700 with 16MB L3 cache, more expensive to manufacture for amd but still usable, and not transformed in one low end product, it would at least hit middle range segment.

Who wants to do the same level of cutting on one of the apple, intel, nvidia, qualcomm, huawei, ... product and get something that is still good enough?

Now about zen5 on tsmc 3nm, and tsmc forcing amd to go first.
Let's assume zen5 chiplet with two 8 core ccx and 64MB L3 cache.
Even doing the same cutting in ~2022 you end up with something usable from the chiplet:
CPU cores #: 8
L3 cache: 16MB

Again using the same three chiplets, it would end up with one very good 16 core cpu with 32MB L3 cache.
This is only trying to justify why tsmc would want amd to go first, of course gpus and apus would have to be out of this 'forcing'.
 
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soresu

Golden Member
Dec 19, 2014
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The zen2 die:

CPU cores #: 8
L3 cache: 32MB
Size: 100% die

Lets hypothetically assume that the tsmc 7nm would have a very bad yield:
CPU cores #: 4
L3 cache: 8MB
Size: 40% good / 60% disabled

Put this on three chiplet packaged and we would be seeing one R7 3700 with 16MB L3 cache, more expensive to manufacture for amd but still usable, and not transformed in one low end product, it would at least hit middle range segment.

Who wants to do the same level of cutting on one of the apple, intel, nvidia, qualcomm, huawei, ... product and get something that is still good enough?

Now about zen5 on tsmc 3nm, and tsmc forcing amd to go first.
Let's assume zen5 chiplet with two 8 core ccx and 64MB L3 cache.
Even doing the same cutting in ~2022 you end up with something usable from the chiplet:
CPU cores #: 8
L3 cache: 16MB

Again using the same three chiplets, it would end up with one very good 16 core cpu with 32MB L3 cache.
This is only trying to justify why tsmc would want amd to go first, of course gpus and apus would have to be out of this 'forcing'.
Ooof, that cache is over 55% of the entire die for only 40 MB!

Come on you slacking MRAM academics, we need an area efficient SRAM replacement!

Of course persistence wouldn't go amiss in mobile use cases either, they could shave some tens to hundreds of milliwatts off that idle power.
 

Gideon

Senior member
Nov 27, 2007
833
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Some very interesting info about Zen4 from GamerNexus from a person they trust who has access to AMD internal roadmaps:

GN usually doesn't speculate with original info and AFAIK if they do their track record has been good.Anyways:

* Zen4 with DDR5 and PCIe4 (not 5) and USB 4, released in 2022 (which makes sense, given the 5Q cadence of AMD)

* Both desktop and mobile APUs will be Zen3+ (first mention) and support DDR5/LPDDR5
 
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tamz_msc

Platinum Member
Jan 5, 2017
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Some very interesting info about Zen4 from GamerNexus from a person they trust who has access to AMD internal roadmaps:

GN usually doesn't speculate with original info and AFAIK if they do their track record has been good.Anyways:

* Zen4 with DDR5 and PCIe4 (not 5) and USB 4, released in 2022 (which makes sense, given the 5Q cadence of AMD)

* Both desktop and mobile APUs will be Zen3+ (first mention) and support DDR5/LPDDR5
In my opinion, what he refers to as Zen3+ for APUs is really a tweaked Zen3, and by tweaked I mean Zen3 with a cut down L3, much like the APUs of today. However it is unknown whether these APUs will be chiplet or monolithic.
 

Hans Gruber

Senior member
Dec 23, 2006
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In my opinion, what he refers to as Zen3+ for APUs is really a tweaked Zen3, and by tweaked I mean Zen3 with a cut down L3, much like the APUs of today. However it is unknown whether these APUs will be chiplet or monolithic.
I looked up what is an APU. One of the responses was a made up name for a CPU with integrated graphics for only one company, (AMD) when they had inferior CPU's before Ryzen. Basically what Intel CPU's offered but with a better Igpu's. A marketing ploy by AMD. It would make sense for AMD to include Vega or something like it in Zen3 or Zen4.

Seriously, who here thinks an APU is something better than a CPU with integrated graphics which is what most Intel CPU's already come with. Obviously, AMD makes GPU's so they could include far superior integrated graphics to Intel.

I don't know if AMD monitors forums but there are quite a few good ideas on anandtech.
 

DrMrLordX

Lifer
Apr 27, 2000
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I wonder if that means Zen4 is 2022 entirely, or if Zen4 will launch on AM4 in 2021 with DDR4 and move to a new socket/new platform in 2022? Either way, I was looking forward to Zen4 + DDR5 in 2021 and now I'm all disappointed. Boo.
 

DisEnchantment

Senior member
Mar 3, 2017
578
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Some very interesting info about Zen4 from GamerNexus from a person they trust who has access to AMD internal roadmaps:
TBH, the only leaks trustworthy these days are software patches and from shillicon gang, (rogame et al). Going forward those leaks will dry up so bad.

A bit tired of hearing Matisse 2, Zen2+ and Zen3+ roadmaps plucked out of thin air.
 
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Topweasel

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Oct 19, 2000
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I looked up what is an APU. One of the responses was a made up name for a CPU with integrated graphics for only one company, (AMD) when they had inferior CPU's before Ryzen. Basically what Intel CPU's offered but with a better Igpu's. A marketing ploy by AMD. It would make sense for AMD to include Vega or something like it in Zen3 or Zen4.

Seriously, who here thinks an APU is something better than a CPU with integrated graphics which is what most Intel CPU's already come with. Obviously, AMD makes GPU's so they could include far superior integrated graphics to Intel.

I don't know if AMD monitors forums but there are quite a few good ideas on anandtech.
It's not a marketing ploy if it is was the sole intention of a 5+ billion dollar acquisition. AMD called it an APU because their eventual goal was some magical world where programmers choose which compute unit (CPU or GPU) they wanted for whatever line of code. It just happened to have first launched just as AMD was losing any semblance of competitiveness on the CPU end.

That said RDNA is less compute friendly then Vega. I could see a world where AMD wants to hold out hope for their Heterogenous computing and continue to use vega. But I doubt that. It will be silly for their work on the consoles to pass up on an opportunity to use it (Navi 2x) in a CPU.
 

DisEnchantment

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Mar 3, 2017
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Heterogenous computing for AMD has gained scope. If you read AMD's presentations, papers and patents, heterogenous processing comprises of FPGA, CPLD, GPU, ASIC, PIM and others besides the CPU.
in my opinion this is a more interesting development in the area of heterogenous computing.

A unified programming paradigm which allow allows seamless work distribution to all these kinds of accelerators will be a game changer. CDNA2 is a big change in programming paradigm for GPU/SIMD accelerated workloads. IMO, it was the factor in AMD's success in winning El Capitan.

Patents indicate that AMD has plans to allow coherency with FPGAs and other ASICs as well. Another wild horse is PIM but not sure how they will integrate this, but it looks like there is considerable work with these too.

1588059460553.png

Imagine having an onboard SRAM based FPGA that you can load the LUTs with whatever config that is suitable for your workload. If you only do video transcoding the FPGA could be loaded with something that can accelerate this by factors of what can be done by a GPU for example.
If AMD ever made enough money I hope they can aquire Xilinx or Lattice Semiconductor or some of the FPGA companies in the future.

Zen4 will be the realization of AMD's long running goal of a true HSA chip. It has been a long ride, from Rick Bergman first presentation of the AMD Fusion APU in 2011 till Zen4 release in 2021/22

 
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