Speculation: Ryzen 4000 series/Zen 3

[trexfromouterspace]

The N5P rumor was stupid to begin with. It should never have picked up any traction.

 

[raghu78]

00810F11h => Raven Ridge
00810F80h => Picasso
00810F81h => Picasso
00820F00h => Raven Ridge 2
00820F01h => Raven Ridge 2

the 60 before the F means it is Renoir.

00860F00h \ Zen2 \ Renoir \ RN-A0 \ 7nm
00860F01h \ Zen2 \ Renoir \ RN-A1 \ 7nm
00860F10h \ Zen2 \ Renoir \ RN-B0 \ 7nm
00860F80h \ Zen2 \ Lucienne \ LN-A0 \ 7nm

Means it is the same die just respun...
FX8100 (Bulldozer): 600F12 <== Zambezi
FX8300 (Piledriver): 600F20 <== Vishera (Same die, new FEOL)
A10 5800K (Piledriver): 610F01 <== Trinity (TN)
A10 6800K (Piledriver): 610F31 <== Richland (RL, Same die, new FEOL)
A10 7850K (Steamroller): 630F01 <== Kaveri, KV (GV, Godavari is probably 630F81)
A10 9700 (Excavator): 660F51 <== Bristol, BR (CZ, Carrizo is probably 660F01)
800F11 <== Summit, ZP
800F82 <== Pinnacle, PiR

Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.

Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).

JESD209-5 => February 2019
JESD209-5A => January 2020

• Additional power reduction functions including WCK power reduction
• Optimized Refresh
• Data/Byte selectable Write X
• Additional SI improvements
• ODT Rank to Rank turnaround improvement
• ODT function for CS pin
• Pin capacitance decrease

Changes added from 5 to 5A spec.

https://valid.x86.fr/nmltsi => Carrizo DDR3, 660F01
http://valid.x86.fr/m49wkt => Bristol DDR4, 660F51
As with these two, it has been done before, thus it can happen again between Renoir and Lucienne.

On another note I have seen mentions for a Zen3 APU for LPDDR5/DDR5/GDDR6 support(it has no support for DDR4 or LPDDR4(x)).
H-models => DDR5(SO-DIMM) or GDDR6(BGA)
U-models => DDR5(SO-DIMM) or LPDDR5(BGA)

Yes your analysis is right about Lucienne being a Renoir refresh (like Picasso was to Raven Ridge). I have done a similar analysis and come to the same conclusion.

https://en.wikichip.org/wiki/amd/cpuid
http://www.cpu-world.com/CPUs/Zen/AMD-Ryzen 7 1700X.html

Eg : Ryzen 7 1700X has a CPU ID of 800F11

Summit Ridge - 800F11
Pinnacle Ridge - 800F82
Matisse - 870F10
Vermeer - A20F00 (https://www.igorslab.de/en/new-deta...us-have-appeared-the-image-is-getting-denser/)


Raven Ridge - 810F10
Picasso - 810F81
Dali - 820F01
Renoir - 860F01 (We know Renoir launched in A1 stepping)
Lucienne - 860F80 (Not yet launched. So stepping could change.)
Van Gogh - 890F00 (Not yet launched. So stepping could change.)
Cezanne - A50F00 (Not yet launched. So stepping could change.)

Naples / TR1 - 800F12
Rome / TR3 - 830F10
Milan / TR4 - A30F00 (Most likely. To be confirmed. Not yet launched. So stepping could change.)

In conclusion all Zen based dies are 800 – 820, Zen 2 based dies are 830-890 and Zen 3 based dies are A20 onwards (A20 - A50, as of now) . There is sufficient information available now to call Lucienne a Renoir refresh with the same die. Cezanne can be confirmed as Zen 3 based next generation APU.

 

[soresu]

Yes your analysis is right about Lucienne being a Renoir refresh (like Picasso was to Raven Ridge).

Picasso was not a mere refresh, it uses the 12nm process node which is similar but different to the 14nm node - it included minor alterations in the Zen+ core and likely some 12nm tweaks and errata fixes to the Vega uArch too.

 

[raghu78]

Picasso was not a mere refresh, it uses the 12nm process node which is similar but different to the 14nm node - it included minor alterations in the Zen+ core and likely some 12nm tweaks and errata fixes to the Vega uArch too.

Picasso used the same Raven Ridge die. There was no change in transistor count, die size and physical design. The same was the case for Pinnacle Ridge vs Summit Ridge. The transistor level improvements from the GF 12nm process brought better freq at iso power and higher peak frequency.

The AMD 2nd Gen Ryzen Deep Dive: The 2700X, 2700, 2600X, and 2600 Tested

www.anandtech.com

 

[soresu]

There was no change in transistor count, die size and physical design.

Keep in mind that transistor counts are rounded up somewhat, minor alterations would not necessarily alter the transistor count to any significant degree.

This is especially true now that we are in the range of billions of transistors per SoC design.

 

[raghu78]

Keep in mind that transistor counts are rounded up somewhat, minor alterations would not necessarily alter the transistor count to any significant degree.

This is especially true now that we are in the range of billions of transistors per SoC design.

Zen + did not involve any physical design changes. To quote from the Ryzen 7 2700x review

"Ultimately, the new processors are almost carbon copies of the old ones, both in terms of design and microarchitecture. AMD is calling the design of the cores as ‘Zen+’ to differentiate them to the previous generation ‘Zen’ design, and it mostly comes down to how the microarchitecture features are laid out on the silicon. When discussing with AMD, the best way to explain it is that some of the design of the key features has not moved – they just take up less area, leaving more dark silicon between other features. "

 

[darkswordsman17]

Update regarding the previous N5P rumor: If AMD is ordering 5nm capacity for autumn this year at TSMC and working on 5nm based products, it is still not publicly mentioning it to investors. Last week AMD updated their corporate presentation, and Zen 3 (slide 13, 30), RDNA 2 (slide 16, 50) and CDNA (slide 18, 31) are all still listed as 7nm.

Not sure why you say that first part. Those slides show they're absolutely working on 5nm based products. There's nothing on there about 5nm this autumn sure, but then there's nothing saying Zen 3 is this autum on there either (wasn't the rumors about that being that it was going to push Zen 3 into 2021?).

I mean, those slides don't mention Zen 2 refresh, does that mean that's not happening? They also didn't have anything about Radeon VII anywhere prior to its announcement. So its not like that absolutely proves anything. Heck those slides don't mention Zen+ so I guess that was all Mandela effect and didn't actually happen?

I've speculated before that 5nm Zen 3 stuff might just be them moving up a Zen 3 refresh that might was supposed to be a cleaner for 5nm Zen 4, while 7nm Zen 3 is server only. So 7nm Zen 3 could still be on track while consumer gets an accelerated Zen 3+ on 5nm earlier. And it could explain why there's no mention of 5nm Zen 3, since they don't mention Zen+ or Zen 2 refresh (whatever it might be called).

Just something to think about.

 

[french toast]

Not sure why you say that first part. Those slides show they're absolutely working on 5nm based products. There's nothing on there about 5nm this autumn sure, but then there's nothing saying Zen 3 is this autum on there either (wasn't the rumors about that being that it was going to push Zen 3 into 2021?).

I mean, those slides don't mention Zen 2 refresh, does that mean that's not happening? They also didn't have anything about Radeon VII anywhere prior to its announcement. So its not like that absolutely proves anything. Heck those slides don't mention Zen+ so I guess that was all Mandela effect and didn't actually happen?

I've speculated before that 5nm Zen 3 stuff might just be them moving up a Zen 3 refresh that might was supposed to be a cleaner for 5nm Zen 4, while 7nm Zen 3 is server only. So 7nm Zen 3 could still be on track while consumer gets an accelerated Zen 3+ on 5nm earlier. And it could explain why there's no mention of 5nm Zen 3, since they don't mention Zen+ or Zen 2 refresh (whatever it might be called).

Just something to think about.

I think the whole N5P thing is a giant myth.
According to this N4 announcement N5P is expected for 2022

TSMC officially reveals its 4nm manufacturing process - Industry - News - HEXUS.net

m.hexus.net

Would be one of the most ambitious moves we have ever seen at this level of manufacturing volume and complexity that I think it is close to zero.

Now a premium apu (ala Kaby G) on low volume to try and squeeze Intel Tigerlake out of premium ultrathin early 2021?..on regular N5... Maybe.. N5P Q4 2020= no chance imo.

 

[Antey]

My speculation for ryzen 4000 product segmentation:

R9 4950X - 16 Zen3 cores. 2 CCDs with 8c each
R9 4900X - 12 Zen3 cores. 2 CCDs with 6c each
R7 4800X - 8 Zen3 cores. 1 CCD with 8c
R7 4700X - 8 Zen3 cores. 2 CCDs with 4c each
R5 4600X - 6 Zen3 cores. 1 CCD with 6c
R5 4600 - 6 Zen3 cores. 2 CCDs with 3c each
R3 4300X - 4 Zen3 cores. 1 CCD with 4c
R3 4100 - 4 Zen3 cores. 2 CCDs with 2c each (i dont know about this one) or 1 CCD with fewer cache?

i think X versions will be better for gaming much like the 3300x is better than the 3100 because of the difference in latencies, other than that i think we will see a bit higher frequencies for the costumers to feel there is a difference (which is not the frequency per se). with series 3000 the X versions were pretty much the same than the normal versions so as we all know they had to lower prices to almost match the normal versions

 

[french toast]

4700x..im sure you meant 2 CCD 4 cores each...yea I agree with all of that, looks good.
Edit. Fixed.

 

[amrnuke]

My speculation for ryzen 4000 product segmentation:

R9 4950X - 16 Zen3 cores. 2 CCDs with 8c each
R9 4900X - 12 Zen3 cores. 2 CCDs with 6c each
R7 4800X - 8 Zen3 cores. 1 CCD with 8c
R7 4700X - 8 Zen3 cores. 2 CCDs with 4c each
R5 4600X - 6 Zen3 cores. 1 CCD with 6c
R5 4600 - 6 Zen3 cores. 2 CCDs with 3c each
R3 4300X - 4 Zen3 cores. 1 CCD with 4c
R3 4100 - 4 Zen3 cores. 2 CCDs with 2c each (i dont know about this one) or 1 CCD with fewer cache?

i think X versions will be better for gaming much like the 3300x is better than the 3100 because of the difference in latencies, other than that i think we will see a bit higher frequencies for the costumers to feel there is a difference (which is not the frequency per se). with series 3000 the X versions were pretty much the same than the normal versions so as we all know they had to lower prices to almost match the normal versions

Cost of 2 chiplets with 3 cores each will be more than 1 chiplet with 2 cores disabled. Making a 4100, 4600 -- and even 4700 -- have two chiplets seems rather wasteful. I don't think they'll have enough CCDs where 4-6 out of the 8 cores are kaput to make this reasonable... unless I'm missing something here.

IMO they continue to down-tier via binning, clocks, possibly cut the L3$ (if defects present in that area) as you mentioned.

I think they'll keep all the 4C-6C chips with 1CCD
I do think an 8C 2CCD chip may have a solid role in compute situations where you want high clocks, lots of L3$, but don't care much about intercore latency.

 

[moinmoin]

Not sure why you say that first part. Those slides show they're absolutely working on 5nm based products. There's nothing on there about 5nm this autumn sure

The whole N5P rumor was about AMD jumping in to fill N5 capacity at TSMC freed by Huawei/HiSilicon no longer being allowed to order more there. Nobody denied that AMD is working with 5nm. Much of the discussion was about the timing and how realistic was AMD doing what the rumor claims this autumn already, with some even suggesting Zen 3 would be duplicated on that node.

And unlike mere refreshes works with new nodes are a huge financial undertaking so it does matter very much whether investors are being informed about it happening.

 

[amd6502]

R7 4800X - 8 Zen3 cores. 1 CCD with 8c
R7 4700X - 8 Zen3 cores. 2 CCDs with 4c each

Not a chance. They will have at the very least one high and an elite binning category for an 8c/1CCD product. I also see no possible advantage to a 2 CCD 8c; there is no reason there would be so many half functional salvage dies for something like this to happen. It's likely that for Epyc there will be such parts in order to double the L3 per core.

 

[itsmydamnation]

renior looks like a work of art

https://twitter.com/x/status/1271028427378868224

 

[juergbi]

IMO they continue to down-tier via binning, clocks, possibly cut the L3$ (if defects present in that area) as you mentioned.

I think they'll keep all the 4C-6C chips with 1CCD
I do think an 8C 2CCD chip may have a solid role in compute situations where you want high clocks, lots of L3$, but don't care much about intercore latency.

With Zen 3 they could also sell a 10C SKU with two 5C CCDs. I don't know whether this would be worth it, however, they could sell it for a bit more and it would provide clearer separation from the 8C SKUs (where there will already be two variants in the 4000 series: Renoir and Vermeer).

 

[Trovaricon]

Not once has the xxF shared between models have been huge die reforming changes. So, Lucienne pretty much has to be identical to previous versions. Thus, Renoir and Lucienne is the same die. Just like Zambezi<->Vishera, Trinity<->Richland, Kaveri<->Godavari, Carrizo<->Bristol, Raven<->Picasso, Summit<->Pinnacle, etc so on so forth.Renoir as far as my deep dive does support LPDDR5, but since it doesn't support DDR4 ECC(144-bit({64+8} x 2) PHY) it might not support DDR5 ECC(160-bit({32+8} x 4) PHY). I am not sure if DDR5 supports ECC-less implementations. If it does it also supports DDR5 up to 6400 Mbps.

Renoir uses the DCT IP w/ LPDDR5/LPDDR4X/LPDDR4 and no-ECC DDR5(if possible)/DDR4 combo phy/controller. Do to the January 2020 update for the LPDDR5 spec, it was probably delayed(to Lucienne) or canned(for Renoir).

What is the information source, that memory controller on Renoir die does not support DDR4 unbuffered ECC? Until now (up to Picasso die), it was simply disabled for non-Pro APU SKUs - meaning product segmentation limitation, not hardware.

 

[Veradun]

With Zen 3 they could also sell a 10C SKU with two 5C CCDs. I don't know whether this would be worth it, however, they could sell it for a bit more and it would provide clearer separation from the 8C SKUs (where there will already be two variants in the 4000 series: Renoir and Vermeer).

My hope is they're going to segment skus on cores alone removing doubles from the lineup (3600 and 3600X, 3700 and 3800X).

 

[amrnuke]

With Zen 3 they could also sell a 10C SKU with two 5C CCDs. I don't know whether this would be worth it, however, they could sell it for a bit more and it would provide clearer separation from the 8C SKUs (where there will already be two variants in the 4000 series: Renoir and Vermeer).

And it would provide nice high-end competition with the 10900K. Though I have reservations, mostly about whether interchiplet latency would hold it back. Would be a really interesting product if it rolls in at $429-449 or so (keeping in mind price of old stock of 3900X).

 

[Ajay]

With Zen 3 they could also sell a 10C SKU with two 5C CCDs. I don't know whether this would be worth it, however, they could sell it for a bit more and it would provide clearer separation from the 8C SKUs (where there will already be two variants in the 4000 series: Renoir and Vermeer).

There was talk about using odd numbers of core complexes, but apparently it's not possible - seem to recall it's an issue with SME policy.

 

[randomhero]

There was talk about using odd numbers of core complexes, but apparently it's not possible - seem to recall it's an issue with SME policy.

You mean different number of cores in ccx within same ccd?
Yes, that should affect zen and zen2 architectures.
But with zen3s rumoured 8 core ccx/ccd that should not be the case. So you could be able to run two five core ccx/ccds. It should be no different than todays 12 core parts.
That is my understanding of that matter.

 

[Ajay]

You mean different number of cores in ccx within same ccd?
Yes, that should affect zen and zen2 architectures.
But with zen3s rumoured 8 core ccx/ccd that should not be the case. So you could be able to run two five core ccx/ccds. It should be no different than todays 12 core parts.
That is my understanding of that matter.

I wrote 'complexes' which means ccx. Zen3s unified L3 cache won't affect this unless the SME policy at play is also changed. For example, that policy may be in place to avoid a possible exploit , in which case it wouldn't change.

Edit: and I was wrong, apparently AMD can disable an odd number of cores per CCX, which still results in an even pair of cores per CCD

 

[randomhero]

I wrote 'complexes' which means ccx. Zen3s unified L3 cache won't affect this unless the SME policy at play is also changed. For example, that policy may be in place to avoid a possible exploit , in which case it wouldn't change.

Edit: and I was wrong, apparently AMD can disable an odd number of cores per CCX, which still results in an even pair of cores per CCD

It's OK buddy .

 

[RetroZombie]

Edit: and I was wrong, apparently AMD can disable an odd number of cores per CCX, which still results in an even pair of cores per CCD

Are you sure about that.
After the R3 3300X release only proved that the amd Ryzen 5 1500X (or 1400X) would be better with just one CCX enabled but they didn't do it at the time because of some technical limitation?

 

[jamescox]

@jamescox No chiplets for APUs, because they'll have to create another configuration.

The best we'll see is a Kaby-G style chip.

That is what I meant. An APU (no separate chipset) plus optional gpu chip and optional HBM chip.

I don’t actually like calling AMD’s multi-chip designs “chiplets”. They are really just MCMs; multi-chip modules. MCMs are not new; I assume that there have been many types of MCMs before this. IBM Power 5 with, if I am remembering correctly, 4 cpu chips and 4 cache chips were around a long time ago. I kind of think that “chiplet“ should specifically refer to die made to be mounted on a silicon interposer not just chips in an MCM.

 

[IntelUser2000]

I don’t actually like calling AMD’s multi-chip designs “chiplets”. They are really just MCMs; multi-chip modules.

I know. But its become a common name. It's like how everyone calls anything RC "Drones", when it should really mean those with some intelligence.