Absolutely nothing like this exists on the next-gen consoles.
It was a reply to this:
darkswordsman17: " There was also a report that Microsoft had Xbox dev units that could do 3 threads per core via some special code path."
Which is a reference to the Hyperscheduler_mode=Enabled and SMT_mode=disabled.
Logical processors = 8
Hs_mode0 = 8(logical)+8(hyperscheduled threads)
Hs_mode1 = 8(logical)+16(hyperscheduled threads)
Hs_mode2 = 8(logical)+24(hyperscheduled threads)
A hyper scheduler is an architectural device that supposedly can accelerate context switching and better support concurrent contexts. In the context from the "leak", AMD/Microsoft was using this to improve consistency of multithreading performance.
Using Zen as an example:
SMT_mode = flat 96(T0) and 96(T1)
HS_mode0 = 192(T0) or 96(T0) and 96(T1) when SMT is needed.
HS_mode1 = " " " or 64(T0) and 64(T1) and 64(T2) when SMT3 is needed.
HS_mode2 = " " " " " or 48(T0) and 48(T1) and 48(T2) and 48(T3) when SMT4 is needed.
=> Fetch windows are tracked in a 64-entry (32 entries in SMT mode) FIFO from fetch until retirement.
=> In SMT mode each thread has 10 dedicated IBQ entries.
=> The op cache is organized as an associative cache with 32 sets and 8 ways. At each set-way intersection is an entry containing up to 8 instructions, so the maximum capacity of the op cache is then 2k instructions. The actual limit may be less due to efficiency considerations. Avoid hot code regions that approach this size for a single thread or half this size for two SMT threads.
=> The op cache is organized as an associative cache with 64 sets and 8 ways. At each set-way intersection is an entry containing up to 8 instructions, so the maximum capacity of the op cache is then 4K ops. The actual limit may be less due to efficiency considerations. Avoid hot code regions that approach this size for a single thread or half this size for two SMT threads.
=> The retire queue can hold up to 192 micro ops or 96 per thread in SMT mode.
=> The retire queue can hold up to 224 micro ops or 112 per thread in SMT mode.
=> It is expensive to transition between single-threaded (1T) mode and dual-threaded (2T) mode and vice versa, so software should restrict the number of transitions. If running in 2T mode, and one thread finishes execution, it may be beneficial to avoid transitioning to 1T mode if the second thread is also about to finish execution.