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Speculation: Ryzen 4000 series/Zen 3

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Tuna-Fish

Golden Member
Mar 4, 2011
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AMD won't do DDR5 on Zen 4 simply because DDR4 has way more market share and it would be easier for consumers to just use their existing DDR4 with a new Zen 4 processor. I don't think either AMD or Intel would go to DDR5 before 2021.
As stated gazillion times already, one of the big advantages of the chiplet architecture with the memory controller on the IO die is that they can sell the same CPU chiplet on two different sockets with different IO dies, allowing them to sell both DDR5 and DDR4 cpus in a single generation. I thing it would be downright weird if AMD doesn't try being a DDR5 early adopter. Anyone who thinks DDR5 isn't worth the premium can still buy the newest AMD CPUs, so they lose nothing by doing so.
 
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moinmoin

Platinum Member
Jun 1, 2017
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DDR5 is definitely coming to the next socket. With PCIe 4.0 I/O bandwidth is already surpassing memory bandwidth which is not a good balance, and the next socket likely introduces (or at least prepares for) PCIe 5.0 as well, again doubling I/O bandwidth.

A more interesting upgrade would be Zen 4 IMO. AMD cannot use the same IOD from Zen3 which is, most likely, largely similar to Zen2 as shown in the slides from UKRI.
They have to solve idle power used by IF which the IOD has a lot of.
I would suppose AMD would have been thinking of countering the Cove Cores, so if they want to have a good chance of fighting back they need some good gains not only in the CCD but also IOD.

I wonder if GF 12LP+ would be a candidate, but with all the rumors and patents of some form of memory stacking it would not surprise me if AMD drops GF at this point in time 2021 time frame.
The idle power used by IF is directly related to the I/O capability offered, such features are hard to power gate unless disabling them outright. Epyc/Threadripper will stay fat idle power wise. The AM4 platform so far has been sitting between chairs, technically having one quarter of Epyc's I/O capability and as such idle power usage, but also being the platform for mobile optimized chips. Ideally AMD would split it in two platforms, one for making the most out of the 32 PCIe lanes (lower end workstations), the other for efficiency optimized APUs from mobile space (all in ones, SFF, NUCs). Renoir reportedly (finally) supporting LPDRR4X may point to such a split.
 

Guru

Senior member
May 5, 2017
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As stated gazillion times already, one of the big advantages of the chiplet architecture with the memory controller on the IO die is that they can sell the same CPU chiplet on two different sockets with different IO dies, allowing them to sell both DDR5 and DDR4 cpus in a single generation. I thing it would be downright weird if AMD doesn't try being a DDR5 early adopter. Anyone who thinks DDR5 isn't worth the premium can still buy the newest AMD CPUs, so they lose nothing by doing so.
You are in your ivory tower. Companies don't think like that, its what is going to be the easiest and cheapest and cleanest way to do this?

Consumers would be so confused by having some Zen 3 chips running at DDR4 and others at DDR5. It would be a mess. If just 1% of millions of customers screw up the ram, it would cause such issues for AMD.

They are not going to use DDR5 before 2021, probably even later!
 

maddie

Diamond Member
Jul 18, 2010
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You are in your ivory tower. Companies don't think like that, its what is going to be the easiest and cheapest and cleanest way to do this?

Consumers would be so confused by having some Zen 3 chips running at DDR4 and others at DDR5. It would be a mess. If just 1% of millions of customers screw up the ram, it would cause such issues for AMD.

They are not going to use DDR5 before 2021, probably even later!
Traditionally, Intel often pioneered using the latest ram. Do you expect AMD to cede this marketing point.

The apparent maxing out of memory bandwidth with the TR 64C supposedly needing 8 ram channels and the 32C relegated to the 4 channel chipset. We should take this to mean faster ram needed sooner rather than later.
 

NTMBK

Diamond Member
Nov 14, 2011
9,401
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Why the Xbone X - that has a much larger GPU compared to the base Xbone, and GDDR5 as opposed to DDR3 if memory serves me correctly.

Anyway, here's some power consumption figures for both.

The base Xbone would probably be just fine for a handheld, we're talking about Jaguar cores and a 12 CU GPU. Though... it'd make no sense over Renoir.

The Xbone-X I don't think would fit into a 35W TDP. Which is already too high for a handheld.
It would make sense from a compatibility point of view, though maybe a single Zen2 cluster could handle it just fine.
 

soresu

Golden Member
Dec 19, 2014
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It would make sense from a compatibility point of view, though maybe a single Zen2 cluster could handle it just fine.
If the point is compatibility they would always go that way given the option for something running the same SW.

Given the point of Jaguar was mobile anyway, it should be fine for the job at the original 1.6 ghz.
 
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NTMBK

Diamond Member
Nov 14, 2011
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If the point is compatibility they would always go that way given the option for something running the same SW.

Given the point of Jaguar was mobile anyway, it should be fine for the job at the original 1.6 ghz.
It would be so good. And the same small, low power chipset could power a ultra-low-end XBox One console, a tiny downloads only box.
 

soresu

Golden Member
Dec 19, 2014
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Not strictly AMD, but it foretells the shape of things to come.

Intel is embedding MRAM as L4 cache apparently.

Link here.
 

Veradun

Senior member
Jul 29, 2016
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It might be included in Zen3 only for EPYC in 2020, since they now have this stuff in a dedicated IOD not shared with desktop :>
 

soresu

Golden Member
Dec 19, 2014
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Looks like Hynix at least anticipates a 2020 release schedule.
It might be included in Zen3 only for EPYC in 2020, since they now have this stuff in a dedicated IOD not shared with desktop :>
Still a relatively short schedule for such a significant part of the IO.

I could see late 2021, but 2020 seems a bit rushed unless it's like WiFi standards where the draft is basically there already.
 

DisEnchantment

Senior member
Mar 3, 2017
904
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Not strictly AMD, but it foretells the shape of things to come.

Intel is embedding MRAM as L4 cache apparently.

Link here.
AMD has so many patent applications related to memory stacking, its far too many to be something that they have no intention of implementing in silicon. One of the most interesting things is that every new patent seems like they are closer to something that can be manufactured.

Besides the many patents that I have listed before, This is a very new one related to a 3D chip with manufacturing techniques for memory stacks on top of processor dies.

20190326272 OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

Untitled1.png
 
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Richie Rich

Senior member
Jul 28, 2019
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Another interesting thing regarding the AMD presentation about Milan SMT2 and unified L3 cache. AdoredTV claims that in his earlier leaked version of that slide there was SMT4 originally.

There is two possible explanation why AMD changed that at SMT2:
  • AMD didn't want to reveal a killer feature like SMT4 at this Zen 2 event (way too early before Zen 3 unveiling)
  • AMD will disable SMT4 for whole Zen 3 generation (due to performance issues due to FPU bottleneck? Zen 4 on 5nm could solve this)


 

Richie Rich

Senior member
Jul 28, 2019
470
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Yea, sure SMT4, 6GHz and $300 price tag. Been there...
You seem pretty confident that SMT4 isn't happening with Zen 3. So how much money would you bet on that? Would you bet your annual income that Zen 3 isn't SMT4? Are you so confident still? Probably not. It's easy to be hero behind keyboard without any responsibility.

My bet is 60:40 for new wider and/or SMT4 core for Zen 3. It's doable, technology is already developed by others, risk is minimal, AMD has great engineers and they had time to do that. All the puzzles shows AMD is hiding something about Zen 3. The only really confident people about Zen 3 SMT are AMD engineers. Everybody else confident is just keyboard hero.
 
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itsmydamnation

Platinum Member
Feb 6, 2011
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  • AMD didn't want to reveal a killer feature like SMT4 at this Zen 2 event (way too early before Zen 3 unveiling)
  • AMD will disable SMT4 for whole Zen 3 generation (due to performance issues due to FPU bottleneck? Zen 4 on 5nm could solve this)
NO, NO ,NO ,NO ,NO
if you want more ILP you need to load and store more. AMD already has 4 SIMD FPU ports, how many more do you want. But it only has 2 load and 1 store and 3 AGU's.

a Power 9 SMT4 core has:
2x128bit SIMD's
4x64bit FP ports
4xAGU's and 4 ports that can all load or store a cycle

All this SMT4 stuff is just stupid, if ILP only average something like 1.5 on spec why would SMT2 only add ~25% performance given there are 11 pipelines in a Zen core. Because the bottleneck isn't in execution!

You seem pretty confident that SMT4 isn't happening with Zen 3. So how much money would you bet on that? Would you bet your annual income that Zen 3 isn't SMT4? Are you so confident still? Probably not. It's easy to be hero behind keyboard without any responsibility.
How much do you want to bet?
 

soresu

Golden Member
Dec 19, 2014
1,686
871
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You seem pretty confident that SMT4 isn't happening with Zen 3. So how much money would you bet on that? Would you bet your annual income that Zen 3 isn't SMT4? Are you so confident still? Probably not. It's easy to be hero behind keyboard without any responsibility.

My bet is 60:40 for new wider and/or SMT4 core for Zen 3. It's doable, technology is already developed by others, risk is minimal, AMD has great engineers and they had time to do that. All the puzzles shows AMD is hiding something about Zen 3. The only really confident people about Zen 3 SMT are AMD engineers. Everybody else confident is just keyboard hero.
The problem that ATV and yourself seem to be discounting is that a leak can contain elements of truth without being wholly truthful, perhaps some of these information dispersals are intentionally planted within companies like AMD to identify leakers when they are suspected to exist - it's what I would do.
 

amrnuke

Golden Member
Apr 24, 2019
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The problem that ATV and yourself seem to be discounting is that a leak can contain elements of truth without being wholly truthful, perhaps some of these information dispersals are intentionally planted within companies like AMD to identify leakers when they are suspected to exist - it's what I would do.
Yes. That's the problem with ATV and others just throwing rumors around and speculating and trying to read tea leaves.

If you throw enough poop at the wall, it will get dirty. And as long as the wall is dirty, they claim to have been right, no matter how big the pile of crap is on the floor.
 

H T C

Senior member
Nov 7, 2018
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The problem that ATV and yourself seem to be discounting is that a leak can contain elements of truth without being wholly truthful, perhaps some of these information dispersals are intentionally planted within companies like AMD to identify leakers when they are suspected to exist - it's what I would do.
They may well be using "well known youtubers" to achieve this: dispersing slightly different info between them in order to pinpoint where exactly the leaks are coming from.
 
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soresu

Golden Member
Dec 19, 2014
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They may well be using "well known youtubers" to achieve this: dispersing slightly different info between them in order to pinpoint where exactly the leaks are coming from.
Pretty much my thought - though what exactly they hope to gain from leaking I don't know, unless it first goes to nVidia or Intel for profit before the YT bloggers.
 

Arzachel

Senior member
Apr 7, 2011
903
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Not strictly AMD, but it foretells the shape of things to come.

Intel is embedding MRAM as L4 cache apparently.

Link here.
On the bleeding edge 22nm process node ;)

I thought the endurance on high performance MRAM was still pretty poor but it's been a while since I've paid attention.
 

soresu

Golden Member
Dec 19, 2014
1,686
871
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On the bleeding edge 22nm process node ;)

I thought the endurance on high performance MRAM was still pretty poor but it's been a while since I've paid attention.
There seem to be several different types of MRAM, not to mention different variants of those types - like STT MRAM has had several revisions that have improved switching speed, density and stability/retention.

I think cell endurance is not the problem so much as data retention - it is technically NVM but retention varies wildly between the types and variants of them.

Not that it is as bad a problem as is made out by some - even if a cell only retains data for a few hours, you can still refresh the data at that point before loss occurs, and it would still be saving a lot of power that is otherwise spent on constantly refreshing/powering DRAM and SRAM when in use.

*For reference, SOT MRAM has been reported with a retention time of 10 years - not indefinite, but a huge power saving on keeping that memory constantly powered if nothing significant is changing.
 

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