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Speculation: Ryzen 4000 series/Zen 3

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NostaSeronx

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You're directly implying that TSMC won't fab for AMD in the future, if AMD's architecture designs aren't up to TSMC (as a CPU customer) wishes.
TSMC can't cancel accepted orders unless the customer fails to pay. However, they can stop accepting purchase orders which equates to a cancellation.
You are basically implying a severely unequal relationship here, with TSMC benefiting far more than AMD.
The chiplet design at AMD benefits AMD more than TSMC. Which can mean TSMC is losing non-chiplet levels of revenues from AMD. So, TSMC benefits from getting processors that assist in the push towards smaller nodes(Like, 5nm's SiGe/t-Si PMOS/NMOS and Graphene-caps in BEOL). AMD benefits as they don't have to buy a fixed amount of wafers from TSMC. Supporting GlobalFoundries is also a big no-no for TSMC, but it can be overlooked if they get "first" status.
 

soresu

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Dec 19, 2014
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The chiplet design at AMD benefits AMD more than TSMC.
Nonsense, AMD is getting more usable product per wafer, but clearly as they are constrained to fulfill market desire for Zen2, there will still be more than enough wafers ordered to keep TSMC happy.

TSMC is a fab company - it is their business to fab silicon designs, not to demand that AMD fab larger designs that will yield less, as monolithic almost certainly will.

In short it is none of TSMC's business how their customers design things, they set a price per wafer and that is the end of it.
 

soresu

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Supporting GlobalFoundries is also a big no-no for TSMC, but it can be overlooked if they get "first" status.
This is likely a thing TSMC would never get from AMD or any customer with sense.

For future security you need to have the flexibility of at least one other fab partner at AMD's size of business.
TSMC can't cancel accepted orders unless the customer fails to pay. However, they can stop accepting purchase orders which equates to a cancellation.
Again, revenue is revenue - if TSMC refused to fab for AMD they would go elsewhere, and future relations with AMD would be soured to a very drastic degree, somewhat similar to MS and Sony's previous experience with nVidia over console GPU's from what I've heard.

If AMD walked away from TSMC, that would not be an insignificant revenue hit at their current resurgent level - TSMC's board members and shareholders would likely prefer that revenue to whatever tech benefits they could force out of AMD (which seems highly dubious).
 

NostaSeronx

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Sep 18, 2011
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In short it is none of TSMC's business how their customers design things, they set a price per wafer and that is the end of it.
Yes, it is... TSMC won't fab anything that yields below 65% by HVM. They have really high standards at what and what can't be fabbed.
This is likely a thing TSMC would never get from AMD or any customer with sense.
They got it from Nvidia, Apple, Qualcomm, and a bunch of others. However, the weight of demand is less as they are all pretty much profitable. AMD is on a wire. If they get passed by Intel or Zhaoxin(TSMC customer), or if ARM/RISC-V(TSMC customers) becomes the big new thing. It will then be time to cut that wire, like they did with Bitmain. They were forced into good faith wafer commitments.

Ultimately, AMD is getting on 5nm sooner. With potential sampling occurring in 1H2020 and socket(AMx/TRx) customers getting 5nm Zen in 2H2020 or "back on schedule" in January 2021.
 
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CentroX

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Apr 3, 2016
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Ryzen 4XXX is Vermeer, and I hearing from a rumor that IPC increase will be at 15%, putting Intel to shame.
 

Trumpstyle

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Jul 18, 2015
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Hot and spicy rumor, get out your table salt.

AMD has canned all 7nm+(7nm EUV) projects that are APU/CPU/GPU 2.5D/3D. AMD instead will be launching them on the 5nm node at the soonest.

7nm DUV, 7nmP DUV, 5nm EUV is the new timeline from an unnamed individual from TW.

Stuff to watch out for: RRD. Three new CCDs at TSMC. Of which one is for the new Renoir(7nm) and its successor Rembrandt(5nm). The D one is for a semi-custom project on 6nm(not AMD mainline, however it might get pushed to 5nm).

TSMC doesn't like the 7nm/7nm+ as first customer, so they want AMD to be on 5nm.
Does this include next-gen consoles from Sony/Microsofts APU's? Do you know what node they are using?
 

NostaSeronx

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Sep 18, 2011
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Does this include next-gen consoles from Sony/Microsofts APU's? Do you know what node they are using?
They are 7nm or 7nmP. The only things affected are 7nm+ chips from AMD directly. The changes are mostly invisible and Microsoft/Sony aren't affected. They can go 7nm+, but AMD is expected to be on 5nm.

Holiday 2020(Q4'2020) => AMD should be launching 5nm(either, paper or actual) and Sony/Microsoft would be launching 7nm.
[NostaExpects for 5nm: Genesis(HEDT CPU)/1st -> Vermeer(DT CPU)/2nd -> Genoa(EPYC)/3rd -> Rembrandt(APU)/4th -> D-----(APU/Semi-custom)/5th]
 
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soresu

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Dec 19, 2014
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They are 7nm or 7nmP. The only things affected are 7nm+ chips from AMD directly. The changes are mostly invisible and Microsoft/Sony aren't affected. They can go 7nm+, but AMD is expected to be on 5nm.

Holiday 2020(Q4'2020) => AMD should be launching 5nm(either, paper or actual) and Sony/Microsoft would be launching 7nm.
[NostaExpects for 5nm: Genesis(HEDT CPU)/1st -> Vermeer(DT CPU)/2nd -> Genoa(EPYC)/3rd -> Rembrandt(APU)/4th -> D-----(APU/Semi-custom)/5th]
Genoa is Zen4/Ryzen 5000 generation, Milan is the server variant for Zen3/Vermeer/Ryzen 4000.

You may have your wires crossed, it is entirely possible that Zen4 will be 5m EUV, but the lack of confirmation of this on the roadmap puts this is question, at least for Zen4.

Meanwhile 7nm+ was confirmed for Milan/Zen3 well before Zen2 came out.
 

NostaSeronx

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Sep 18, 2011
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Meanwhile 7nm+ was confirmed for Milan/Zen3 well before Zen2 came out.
However, we got confirmation in a roadmap with Milan that it is 7nm, not 7nm+.

Milan is Family 17h, thus Zen.
Genesis/Genoa/Vermeer is Family 19h, thus post-Zen: Next Meditation (or "Cultivation" in Chinese) Core
 
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NostaSeronx

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Sep 18, 2011
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It's all there in black and white as they say:
That is the wrong roadmap:
AMD_EPYC_Zen_CPU_Architecture_Roadmap_1030x579.jpg

Do you think the new hire would allow a mistake within six months in the job? Milan isn't 7nm+, it is 7nm. 7nm+ isn't design rule compatible, thus everything has to be redesigned. The only two nodes that support same design rules are N7P and N6.

Milan is Family 17h, with it possibly being Models 40h-4Fh(Starship2). Vermeer however isn't a Family 17h SKU(It isn't Family 17h 80h-8Fh), it is a Family 19h SKU, with models being 20h-2Fh. This is followed by Genesis which also happens to be Genoa being Family 19h Models 00h-0Fh.
 
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Gideon

Golden Member
Nov 27, 2007
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View attachment 12228

Do you think the new hire would allow a mistake within six months in the job? Milan isn't 7nm+, it is 7nm. 7nm+ isn't design rule compatible, thus everything has to be redesigned. The only two nodes that support same design rules are N7P and N6.
Yes, it's true that 7nm and 7nm+ have incompatible design rules (unlike 6nm) but so what? Milan has been marked as 7nm+ for years. AMD has always designed it for that node, just look at this slide (source) from 2017:



But I guess it's all FUD, and we are really getting GloFo 22nm FD-SOI Bulldozer successors?
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Yes, it's true that 7nm and 7nm+ have incompatible design rules (unlike 6nm) but so what? Milan has been marked as 7nm+ for years. AMD has always designed it for that node, just look at this slide (source) from 2017:
Irrelevant as it is referencing 7LP(DUV), 7LP+(DUV), 7LP+EUV, back then. Roadmaps change without notice, and 7nm+ is the thing changing.
 
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soresu

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Dec 19, 2014
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Do you think the new hire would allow a mistake within six months in the job? Milan isn't 7nm+, it is 7nm. 7nm+ isn't design rule compatible, thus everything has to be redesigned. The only two nodes that support same design rules are N7P and N6.
It's my impression that this slide was meant to convey 2 specific things only - that Milan/Zen3 only has SMT2 (thereby dispelling SMT4 rumours), and that it has a unified L3 CCD with a possible density increase beyond 32 MB (a teaser to placate the masses of hard SMT4 shippers bereft of all hope from the SMT2 revelation).

Basically it implies a very close physical layout to Rome, with a sprinkling of cache related teasers - that is it, and then only to tide the slavering monsters like us over a few months while we feast upon it and give their poor PR department some room to breath (they really do try so hard).
 

Gideon

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Nov 27, 2007
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It's my impression that this slide was meant to convey 2 specific things only - that Milan/Zen3 only has SMT2 (thereby dispelling SMT4 rumours), and that it has a unified L3 CCD with a possible density increase beyond 32 MB (a teaser to placate the masses of hard SMT4 shippers bereft of all hope from the SMT2 revelation).

Basically it implies a very close physical layout to Rome, with a sprinkling of cache related teasers - that is it, and then only to tide the slavering monsters like us over a few months while we feast upon it and give their poor PR department some room to breath (they really do try so hard).
And the cache might actually still be the same 32MB. A while back (when AMD got it's first HPC wins for zen3, before zen2 was out) AMD also referenced Milan as having <=64 cores. I guess, they just didn't want to give too much away.
 

soresu

Golden Member
Dec 19, 2014
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Milan is Family 17h, with it possibly being Models 40h-4Fh(Starship2). Vermeer however isn't a Family 17h SKU(It isn't Family 17h 80h-8Fh), it is a Family 19h SKU, with models being 20h-2Fh.
The only way this makes sense is if AMD only makes Zen3 for server, and no desktop part is made.

Vermeer has been seen on a roadmap as the 2020 desktop successor to Matisse, so unless Vermeer skips Zen3 and goes to Zen4 your statement makes zero sense.

1571661859802.png

Everything that has launched so far and had pre emptive Linux code drops (Renoir) supports this roadmap.

Unless Vermeer is just a Zen2/Matisse refresh of course (I doubt it, I only put that because neither new core is listed underneath it, nor Zen3 mentioned).
 
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soresu

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AMD also referenced Milan as having <=64 cores. I guess, they just didn't want to give too much away.
<=64 means "less than or equal to 64", which matches the new slide with unified L3 CCD in Milan.

Edit: Nevermind that comment, I often misread tense if I read things too quickly, I thought you wrote "AMD previously referenced".
 
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soresu

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Dec 19, 2014
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And the cache might actually still be the same 32MB. A while back (when AMD got it's first HPC wins for zen3, before zen2 was out) AMD also referenced Milan as having <=64 cores. I guess, they just didn't want to give too much away.
It may well be that 32 MB is the standard part, with HPC customers being given the option of a larger L3 cache semi custom variant.

Though given it's new unified nature that sounds like a severe ballache to engineer for a few customers, even for tens of thousands of chips per customer.
 

NostaSeronx

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Sep 18, 2011
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Vermeer has been seen on a roadmap as the 2020 desktop successor to Matisse, so unless Vermeer skips Zen3 and goes to Zen4 your statement makes zero sense.
Unless Vermeer is just a Zen2/Matisse refresh of course (I doubt it, I only put that because neither new core is listed underneath it, nor Zen3 mentioned).
Vermeer/Genesis isn't in Family 17h, so it isn't Zen anymore.
Milan/Renoir however are Family 17h, so they are still Zen.

Automatically, that should tell you Vermeer and Genesis aren't Zen3.
 

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