Speculation: Ryzen 3000 series

[DrMrLordX]

So this was basically a soft launch, with limited availability. Newegg is already sold out of 3700x and 3900x, and I don't even see the 3800x.

We don't know. Everyone sold out fast on the 3900x. It appears as though supplies of anything but the 3600/3600x were restricted, but unless we have numbers, nobody can tell.

So, how many zen 2 were sold just today if stocks are more&less limited?

We don't know.

Does the 3700 hitting its max power constraints under normal operation imply there would be virtually no overclocking headroom?

That's a misnomer. Watch der8auer's delid vid (it's in the benchmark thread) but I will break it down in my own language.

We saw this effect with Radeon VII: lower the temps, and you CAN get higher clocks (if you want them) without adding voltage. Cooling = headroom. Period. Matisse is the same way. You get more clockspeed headroom at 30C than you do 50C than you do 70C, and it is measurable. Same voltage, higher clocks. On Matisse, this effect is observable up to around 5 GHz (give or take) after which point the chip will stop scaling due to either process limits or cold bug. You're talking heavy negative temps there.

Then there's this:

https://forums.anandtech.com/threads/ryzen-3000-series-benchmark-thread-open.2566782/post-39863859

This review also sort-of showed the same effect, where he put a 3700x on a simple watercooling loop with one rad (think it was a 360) with no fans. He dunked the rad in icewater and got extra clockspeed at stock running Cinebench.

With Piledriver, the old saying used to be: if you can cool it, you can clock it. With Matisse, if you can cool it, it clocks itself.

 

[Tuna-Fish]

Yeah. These things love water.

 

[itsmydamnation]

Yeah. These things love water.

Chilled water

 

[moinmoin]

So since this is the speculation thread, is there any review using the latest Windows update, using AGESA 1.0.0.3AB and have both UEFI CPPC2 and PBO confirmed working? Or what is still WIP after the launch?

 

[IEC]

So since this is the speculation thread, is there any review using the latest Windows update, using AGESA 1.0.0.3AB and have both UEFI CPPC2 and PBO confirmed working? Or what is still WIP after the launch?

Your guess is as good as mine. Lots of unanswered questions.

 

[DrMrLordX]

So since this is the speculation thread, is there any review using the latest Windows update, using AGESA 1.0.0.3AB and have both UEFI CPPC2 and PBO confirmed working? Or what is still WIP after the launch?

Most of the reviewers did not say which AGESA version was available to them at the time of their review.

 

[DarthKyrie]

Chilled water

We could always borrow Intel's chiller.

 

[DrMrLordX]

We could always borrow Intel's chiller.

I know you're joking, but you may be bringing up an interesting point (by accident). You wouldn't need that massive chiller. Intel's 28c was dumping an enormous amount of heat. der8auer claims that his 3900x didn't require more than 180W (???) under LN2. Total heat dissipation requirements aren't that high. You just need to get the temps low. In my opinion, this is an excellent opportunity for people to experiment with TECs. They're annoying because of the additional heat output, but they're quite useful for getting something cold when your heat source isn't producing that much heat flux.

 

[DarthKyrie]

I know you're joking, but you may be bringing up an interesting point (by accident). You wouldn't need that massive chiller. Intel's 28c was dumping an enormous amount of heat. der8auer claims that his 3900x didn't require more than 180W (???) under LN2. Total heat dissipation requirements aren't that high. You just need to get the temps low. In my opinion, this is an excellent opportunity for people to experiment with TECs. They're annoying because of the additional heat output, but they're quite useful for getting something cold when your heat source isn't producing that much heat flux.

I was joking but at the same time I was serious, I would love to see what someone could achieve with a chiller as Intel had.

 

[DrMrLordX]

I was joking but at the same time I was serious, I would love to see what someone could achieve with a chiller as Intel had.

I would rather see someone revisit the "beer fridge PC" concept, albeit taken more-seriously. Refrigerators aren't built for those kinds of heat loads or duty cycles.

 

[zinfamous]

I think my ~30 day-old sell order of $35/share will hit tomorrow.


....at least I maintained some shares in reserve. Just because.

 

[lopri]

Microcenter has 3200G and 3400G in stock. Does anyone know what these are?

 

[Hitman928]

Microcenter has 3200G and 3400G in stock. Does anyone know what these are?

Zen+ cores. Basically 2200G/2400G with a clock bump and I believe an update for much lower idle power.

 

[DarthKyrie]

Microcenter has 3200G and 3400G in stock. Does anyone know what these are?

Those are the 12nm Zen+ APUs, basically, die-shrunk versions of the 2400G and 2200G with maybe some tweaks but definitely higher clocks.

Edit: Damn Ninjas got me again.

 

[Hitman928]

Those are the 12nm Zen+ APUs, basically, die-shrunk versions of the 2400G and 2200G with maybe some tweaks but definitely higher clocks.

Edit: Damn Ninjas got me again.

, Ninja Vanish!

 

[lopri]

Zen+ cores. Basically 2200G/2400G with a clock bump and I believe an update for much lower idle power.

I see. So those are 12nm parts.

 

[lopri]

Is bus overclocking not a thing anymore?

 

[DarthKyrie]

I see. So those are 12nm parts.

If you are waiting on Zen2 APUs those should be later in the year or early next year, I think it depends on how the NAVI chiplet and the I/O chiplet on 7EUV are doing.

Edit: As a side note on the 7EUV I/O die, I think this is where we are going to start seeing an L4$ on it as well as some extra stuff to control the GPU.

 

[amd6502]

If you are waiting on Zen2 APUs those should be later in the year or early next year, I think it depends on how the NAVI chiplet and the I/O chiplet on 7EUV are doing.

Edit: As a side note on the 7EUV I/O die, I think this is where we are going to start seeing an L4$ on it as well as some extra stuff to control the GPU.

Interesting theory. That would be a good option, to combine a relatively small 7nm GPU (which would be tiny by itself) with an IO chiplet that has some L4.

The one problem I see is that 7nm projects are pricey, and APUs with more than 4c/8t of CPU are still too niche. One might better justify a low(er) budget project such as 12nm/14nm.

I think they will go monolithic for the next mobile oriented APU, which I am guessing might be expected mid year or later in 2020 and be quadcore. That one might be Zen3 (where some speculate SMT4 is on the table, meaning up to 16 threads for a quadcore versus Picasso and RR's 8 threads).

I think there's a good chance there could be chiplet based Zen2 APU before this. This would not be mobile oriented but oriented at both desktop and mobile. The point of this product would be to broaden the product range of APU's beyond quadcore, and thereby complement a monolithic quadcore APU once it arrives (in a year). Regarding such a potential early-arrival chiplet APU possibility:

1. Would it be possible to use the current 12nm IO hub with a GPU chiplet (and the current Zen2 CPU chiplet)? If yes, then probably just couple this with, a 12nm Vega chiplet. Something similar in size to the CPU chiplet (~75mm2) would be about equivalent to Picasso and be able to max out dual channel graphics.

2. If above 1. is not possible the second option: they could make a new 12nm IO hub with an iGPU (anything from 3 to 10 CU of Vega) that would couple with one Zen2 chiplet.

So these are three potential non-monolithic possiblities.

 

[DarthKyrie]

Interesting theory. That would be a good option, to combine a relatively small 7nm GPU (which would be tiny by itself) with an IO chiplet that has some L4.

The one problem I see is that 7nm projects are pricey, and APUs with more than 4c/8t of CPU are still too niche. One might better justify a low(er) budget project such as 12nm/14nm.

I think they will go monolithic for the next mobile oriented APU, which I am guessing might be expected mid year or later in 2020 and be quadcore. That one might be Zen3 (where some speculate SMT4 is on the table, meaning up to 16 threads for a quadcore versus Picasso and RR's 8 threads).

I think there's a good chance there could be chiplet based Zen2 APU before this. This would not be mobile oriented but oriented at both desktop and mobile. The point of this product would be to broaden the product range of APU's beyond quadcore, and thereby complement a monolithic quadcore APU once it arrives (in a year). Regarding such a potential early-arrival chiplet APU possibility:

1. Would it be possible to use the current 12nm IO hub with a GPU chiplet (and the current Zen2 CPU chiplet)? If yes, then probably just couple this with, a 12nm Vega chiplet. Something similar in size to the CPU chiplet (~75mm2) would be about equivalent to Picasso and be able to max out dual channel graphics.

2. If above 1. is not possible the second option: they could make a new 12nm IO hub with an iGPU (anything from 3 to 10 CU of Vega) that would couple with one Zen2 chiplet.

So these are three potential non-monolithic possiblities.

The issue with number 1 is the sizes of the I/O die and the GPU chiplet on 12nm, in order to fit all three with a decent sized GPU chiplet both dies will require a shrink in order to fit. To increase what is available in the I/O die to include a GPU chiplet along with an L4$ would require the shrink from 7EUV in order to fit a consumer platform socket.

The problem with number 2 is also a matter of package size on a consumer platform.

If AMD wanted to today, they could do either of 1 or 2 and release it on the Threadripper platform. They won't due to the costs of the platform.

AMD has already been experimenting with GPU chiplet designs for Video Cards going forward because they know that in order to continue to push things forward GPUs will have to become more modular just like Zen on the CPU side. AMD is fast approaching 2.5D & 3D stacking to start adding DRAM onto the I/O dies along with using TSMC's new tech that is similar to Forveros at Intel for packaging different chips together on 1 package.

 

[TheGiant]

I know you're joking, but you may be bringing up an interesting point (by accident). You wouldn't need that massive chiller. Intel's 28c was dumping an enormous amount of heat. der8auer claims that his 3900x didn't require more than 180W (???) under LN2. Total heat dissipation requirements aren't that high. You just need to get the temps low. In my opinion, this is an excellent opportunity for people to experiment with TECs. They're annoying because of the additional heat output, but they're quite useful for getting something cold when your heat source isn't producing that much heat flux.

I dont like saying I said it but this time -I said it
Heat flow density is going to be a problem with lesser nodes. IMO that is the reason that otherwise excellent Icelake laptop demo with dell xps has a fan!

 

[therealmongo]

Has anybody seen anything out there with regards to overclocking the IF ???

 

[DrMrLordX]

Edit: Damn Ninjas got me again.

DarthKyrie was so young, so full of potential. And now he is lost to the Ninjas. Have they no honor?!?

, Ninja Vanish!

Cowards!

Is bus overclocking not a thing anymore?

Not . . . really. It's been known to promote instability in PCIe devices. Especially many NVMe drives. It also messes up stability if you're using SATA connectors serviced by the SoC. If you use mobo chipset SATA ports only (or worse, you use USB storage connected through the chipset) then you have some leeway. My x370 board can technically OC bclk to 136 MHz. Not that I've ever bothered.

Has anybody seen anything out there with regards to overclocking the IF ???

Nothing yet.

 

[Zucker2k]

I dont like saying I said it but this time -I said it
Heat flow density is going to be a problem with lesser nodes. IMO that is the reason that otherwise excellent Icelake laptop demo with dell xps has a fan!

One other consideration, is chiplet placement. Der8auer touched on this in his delid video.

 

[therealmongo]

Nothing yet.

Thought as much, its something really important for us to know!

Hope we see someone testing this soon