Speculation: Ryzen 3000 series

[Kedas]

I assume the DDR4-5000 MT/s (2.5GHz) support is on half speed IF.
But maybe the point is to reduce power of the IF that you can use to boost the CPU clock more.

I'm sure there are benchmarks that aren't really IF/latency dependent, but like higher clocks (and fit mostly in the big Ryzen 3000 cache.)

 

[cortexa99]

https://translate.google.com/transl...ps://www.chiphell.com/thread-1995461-1-2.html

some guys who close to industry make speculation about Zen2 DRAM OC potencial according to what rumor they heard, Zen2 could be OC 5000Mhz RAM with some good RAM, and it's very possible that first wave shipping of MSI board make this record.

 

[moinmoin]

I may have heard wrong but didn't someone from AMD say during the event when they showed off Epyc2 that IF is now tied to PCIe 4.

Not tied. IF can be used as an interconnect over PCIe 4, like between CPU and GPU as part of Gen-Z and CCIX. The Frontier supercomputer will use such a topology afaik.

 

[RaV666]

So theres 3 things to keep in mind with DDR4.
Actual clock rate which is 133-200Mhz, Actual bus clock which is half of what Memory makers advertise, and the fact that with memory speed we are talking about MT/s and not Mhz .
Anyhow, IF speed is the same speed as the BUS CLOCK, and with zen it can run at half the bus clock which is 4x less than the MT/s number .
I edited it twice to get a simple summary of the thing i wrote a bit wrong before.

 

[Topweasel]

It's okay. I was caught off-guard by the 10x and 10y thing.

Apparently, DRAM manufacture is "stuck" on a 10nm node. So node refinements are all they can achieve. I don't know all the technical details behind it. Anyway, DDR4 as we know it is manufactured on the older 10x node. 10y node should feature higher speeds and lower voltages. There is a vanishingly small amount of 10x DDR4 that can bin for DDR4-5000, but 10y should be a different story.

I myself am sitting on some 10x DDR4-4400 which should be "good enough" for me until DDR5 hits the scene. I hope!



That is something I hope to test. Not sure if my RAM will be up to DDR4-5000 or not, but if Zen2 can handle the XMP settings then I can at least test DDR4-4400. Higher IF speeds will equal lower IF latency, which should in turn improve performance for any workload where intercore latency is a concern.



Actually, no. Check this out:

https://www.transcend-info.com/Support/FAQ-296

JEDEC members have been employing tricks over the years to increase data transfer rate without (necessarily) increasing memory clocks. For example, DDR4-3200 operates at only 200 MHz internally. On a Ryzen system running DDR4-3200, the IF frequency is 1600 MHz, which is eight times that of the memory clock. IF is actually linked to the memory bus clock in this circumstance. If we want to be technical, then, there you have it.

It appears as though most Summit Ridge chips crapped out at an IF speed of around 1066-1233 MHz. Pinnacle Ridge was a bit better, hitting speeds of 1300 MHz for a non-trivial number of overclockers. I am hoping Zen2 can manage at least 2000 MHz IF.

Okay yes I was talking about the actual clock rate of the bus, but I screwed up. But this half rate stuff has been killing me because it acts like AMD had a divider at the time and choose half for whatever reason. It's tied to the memory bus clock synchronously.

 

[Ajay]

So theres 3 things to keep in mind with DDR4.
Actual clock rate which is 133-200Mhz, Actual bus clock which is half of what Memory makers advertise, and the fact that with memory speed we are talking about MT/s and not Mhz .
Anyhow, IF speed is the same speed as the BUS CLOCK, and with zen it can run at half the bus clock which is 4x less than the MT/s number .
I edited it twice to get a simple summary of the thing i wrote a bit wrong before.

Actual clocks for the memory chips themselves are higher than that (min 200mhz, much higher for faster ram). The dram I/0 bus speed which is 4x the memory chip clocks and then the data transfer rate, which is 2x the IO rate. https://en.m.wikipedia.org/wiki/DDR4_SDRAM#JEDEC_standard_DDR4_module

 

[Fanatical Meat]

Biostar X570 spotted, link has real data & good picture too

https://wccftech.com/biostar-x570-racing-gt8-motherboard-amd-ryzen-3000-cpu-leak/

Has a chipset fan too

 

[fleshconsumed]

Well, at least it'll have an option to switch the fan off. Personally, I'd rather put a bigger passive heastink. The space wasted by the fan is the space that could have been used by more heatsink fins.

 

[amrnuke]

Actual clocks for the memory chips themselves are higher than that (min 200mhz, much higher for faster ram). The dram I/0 bus speed which is 4x the memory chip clocks and then the data transfer rate, which is 2x the IO rate. https://en.m.wikipedia.org/wiki/DDR4_SDRAM#JEDEC_standard_DDR4_module

Based on this, as I understand it, DDR4-2933 memory is running at 366.67 MHz, and an 8x = 1466.67 MHz I/O bus speed, DDR brings it to 2933 MT/s. This means IF is running at 1466.67 MHz, correct? The processor of a 2200G runs at 3.5 GHz, with a multiplier of 35, telling me the system FSB is 100 MHz. If this is the case, aren't there huge "sync" issues between the CPU and IF? Wouldn't it be better to "auto-tune" the CPU to match the IF speed? I always imagine it's similar to how 60 Hz TVs have issues with 24 fps media (interpolation reducing fidelity) that the 120 Hz TVs have solved nicely.

Further, wouldn't it be most ideal to have the CPU running "on par" with memory/IF speeds? For example, is there a performance benefit to having memory/IF at 1500 MHz and the CPU at 4500 MHz to sync clock cycles? Or is this not a thing?

 

[IntelUser2000]

Further, wouldn't it be most ideal to have the CPU running "on par" with memory/IF speeds? For example, is there a performance benefit to having memory/IF at 1500 MHz and the CPU at 4500 MHz to sync clock cycles? Or is this not a thing?

It's much more complex than that.

You have the BCLK which runs at 100MHz, which affects frequencies of every component in the system. If you have a 3.5GHz CPU, then the multiplier is x35. But RAM has its own multiplier, and so does PCI Express, etc. DDR4-2933 would then have a multiplier of 14.66x.

It doesn't mean the "system" or BCLK runs everything. The multiplier is just there so everything is synchronized otherwise you have issues with data corruption. CPU and Memory run on their own clocks.

With vision systems, there are tangible benefits like making the visuals not artifact. However for bus, syncing only has benefits for performance. CPU clocks benefit applications more than needing things to sync, so its not bothered.

Needing to sync is more for older CPUs with chipset memory controllers and FSB setups. You wanted to have 1066MHz equivalent RAM(whether x1 1066MHz or x2 533MHz) with a 1066MHz FSB. Rather than 1600MHz RAM with the same 1066Mhz FSB, you'd want to have 2133MHz RAM(since its multiples of the FSB).

 

[amrnuke]

It's much more complex than that.

You have the BCLK which runs at 100MHz, which affects frequencies of every component in the system. If you have a 3.5GHz CPU, then the multiplier is x35. But RAM has its own multiplier, and so does PCI Express, etc. DDR4-2933 would then have a multiplier of 14.66x.

It doesn't mean the "system" or BCLK runs everything. The multiplier is just there so everything is synchronized otherwise you have issues with data corruption. CPU and Memory run on their own clocks.

With vision systems, there are tangible benefits like making the visuals not artifact. However for bus, syncing only has benefits for performance. CPU clocks benefit applications more than needing things to sync, so its not bothered.

Needing to sync is more for older CPUs with chipset memory controllers and FSB setups. You wanted to have 1066MHz equivalent RAM(whether x1 1066MHz or x2 533MHz) with a 1066MHz FSB. Rather than 1600MHz RAM with the same 1066Mhz FSB, you'd want to have 2133MHz RAM(since its multiples of the FSB).

If you can (and I don't know, because the base hardware workings are somewhat foreign to me), is there an easy way to explain why the CPU at 35x wouldn't have a lot of waiting periods for data from IF running at 14.66x?

 

[thigobr]

I remember in the K8 days they used to round the memory clock multiplier to it be an integer multiple... For Ryzen either the way the circuit works is different or under the curtains they still use some rounding.

 

[moinmoin]

If you can (and I don't know, because the base hardware workings are somewhat foreign to me), is there an easy way to explain why the CPU at 35x wouldn't have a lot of waiting periods for data from IF running at 14.66x?

System memory is always much slower than the actual CPU. That's why cache was introduced sitting in between that's much faster (but still not instantaneous).

 

[DrMrLordX]

Based on this, as I understand it, DDR4-2933 memory is running at 366.67 MHz, and an 8x = 1466.67 MHz I/O bus speed, DDR brings it to 2933 MT/s. This means IF is running at 1466.67 MHz, correct?

Not quite.

DDR4-3200 = 200 MHz RAM, 1600 MHz memory bus, 1600 MHz IF link
DDR4-2933 = ~183 MHz RAM, ~1466 MHz memory bus, ~1466 MHz IF link

etc.

 

[Ajay]

Not quite.

DDR4-3200 = 200 MHz RAM, 1600 MHz memory bus, 1600 MHz IF link
DDR4-2933 = ~183 MHz RAM, ~1466 MHz memory bus, ~1466 MHz IF link

etc.

Dram chip clocks are 400 and 366 MHZ respectively.

 

[Asterox]

This new updated information about Ryzen 2 CPU clocks is very expected for TSMC 7nm.

All core turbo is 4.5ghz, singlecore Turbo is
let's assume near 5ghz.

8/16 Ryzen+ 12nm R7 2700X/stock 3.7ghz, all Core Turbo 4ghz, singlecore Turbo 4.3ghz 95W TDP-a

8/16 Ryzen 2 7nm/let's assume stock 4.1ghz, all Core Turbo 4.5ghz, singlecore Turbo 4.8ghz , 65W or 95W TDP i'm not sure

 

[DrMrLordX]

Dram chip clocks are 400 and 366 MHZ respectively.

Negative:

https://www.transcend-info.com/Support/FAQ-296

 

[Fanatical Meat]

This new updated information about Ryzen 2 CPU clocks is very expected for TSMC 7nm.

All core turbo is 4.5ghz, singlecore Turbo is
let's assume near 5ghz.

8/16 Ryzen+ 12nm R7 2700X/stock 3.7ghz, all Core Turbo 4ghz, singlecore Turbo 4.3ghz 95W TDP-a

8/16 Ryzen 2 7nm/let's assume stock 4.1ghz, all Core Turbo 4.5ghz, singlecore Turbo 4.8ghz , 65W or 95W TDP i'm not sure

Leaks are happening, two decent leaks in one day.
The quickening is happening

 

[StinkyPinky]

Good news that the leaks are ramping up, must mean the release date is not that far away! July looking good.

 

[itsmydamnation]

So if they have 12 core x , 16 core non x and 16 core x models and the boosting works the same a Ryzen gen 2 , i expect the 12 core x is going to be the processor to get in terms of overall performance (single +multi thread) vs cost.

 

[Fanatical Meat]

So if they have 12 core x , 16 core non x and 16 core x models and the boosting works the same a Ryzen gen 2 , i expect the 12 core x is going to be the processor to get in terms of overall performance (single +multi thread) vs cost.

That’s what I’m waiting for

 

[StinkyPinky]

Yeah I'm looking at the 12 core also. Really depends on how well the infinity fabric holds up though. That's the key.

 

[Glo.]

4550 Mhz on all core boost for 12 core CPU is very good. It is 250 MHz higher than 8 core Core i9-9900K stuck in 95W TDP mode.

 

[StinkyPinky]

Will be interesting to see if the 12c comes with a cooler.

 

[Markfw]

Will be interesting to see if the 12c comes with a cooler.

With the lower TDP. I am sure they could use the 2700x cooler with no changes.