A TSMC 7nm wafer right now is easily 10+ k and probably closer to 15. What it will be in a few months I don't know.
IIRC TSMC said that in their last quarterly earnings that the ASP of their 16 and lower wafers was around 6k, so you factor that the 16/12 wafers are slightly cheaper than 6k while 10 and 7 are way higher.
If we're assuming that there actually is a Navi GPU chiplet (or Navi main die) then there would be (at least) two possible designs (keeping all previous recent assumptions):
With a small ~72mm² Navi-chiplet
With a larger (~120 mm²) Navi GPU die
Both designs have pros and cons but both would also add to the developing costs of Ryzen 3000 desktop chips. Small Navi-chiplet would have better yields but larger Navi GPU die would have more control over main memory accesses as it would also contain DDR4 memory controllers. I'm too tired to think this anymore and will just leave this here. Please listen and see carefully what AdoredTV had to say and make your own assumptions based on that.
I suggest to keep an open mind for many different possibilities that Ryzen 3000 could be. Since AdoreTV's new video, everything got much less clear all of a sudden. But it's okay and after CES 2019 we shoud know at least a little bit more.
If you have any other suggestions, please share them with us.
I made some comparisons for Summit/Pinnacle Ridge and Raven Ridge using Die Per Wafer Calculator. I used otherwise the same parameters as before but for 14nm I assumed defect density of 0.08 #/mm² and low $3000 cost per wafer as AdoredTV did here. This is nothing new and if you have the time, I suggest to watch some of the older AdoredTV videos where he has some more wafer yield calculations. Anyway, here are the wafer maps:
Both dies are very similar size and if we assume 100% yield (to simplify calculations) and there are 264 dies per wafer then with $3000 wafer cost, the cost per die would be about $11.4. If we assume wafer cost of $6000 then cost per die would be double of the prevous i.e. $22.8. It should be pretty clear that 120mm² die on 7nm would be more expensive to manufacture than 210mm² die on 14nm. By how much, depends on actual wafer costs.
It should still be noted that porting DDR4 memory controllers, PCIe4 and all other IO and uncore stuff to 7nm is not an easy or cheap task. Therefore the original IO die concept made more sense from financial and manufacturing standpoint.
Would a 72mm² chiplet be able contain 8 cores, 2xDDR4 memory controllers, 24-32xPCIe4 and alll other IO? Seems like the chiplet is too small to have all that. Let's hope that we get clearer info a little bit later.
Yes I know that masks themselves may not be that expensive but I mean total developmental cost of the new die with, as you say, the ported ddr4 controllers and what not. Laying out the circuits and validating the whole design will also take time and money.
It only makes sense for AMD to do that if they can expect to sell enough chips to spread the cost and still make a profit.
If AMD spends 100 million developing the new die but can only sell 1 million chips, then the total cost of each chip is 100$ plus whatever it cost to manufacture it.
My point is the cost of each wafer is a fraction of what it took to design the chip and looking at yields and manufacturing cost tells us almost nothing without knowing how much it cost to develop the chip, or how many units AMD expects to sell.
Wasn't there the theory that the IO die is designed in a way it can be easily cut? i assumed that was meant on a design level but maybe it was meant literally. So could any Electrical engineer here explain if this is even remotely a possibility? To design a chip in a way it can be physically cut and still work? So for ryzen they would just use 1/4 of the IO die. Yeah I don't really believe that is feasible but maybe it is?
I however also don't think it's feasible to create these chiplets and then use something different on consumer ryzen..
Wasn't there the theory that the IO die is designed in a way it can be easily cut? i assumed that was meant on a design level but maybe it was meant literally. So could any Electrical engineer here explain if this is even remotely a possibility? To design a chip in a way it can be physically cut and still work? So for ryzen they would just use 1/4 of the IO die. Yeah I don't really believe that is feasible but maybe it is?
I however also don't think it's feasible to create these chiplets and then use something different on consumer ryzen..
Haven't graduated yet but it's definitely feasible if the chip has 4 modular parts with standardized connections. Just cut them along those lines and connect the pins to something else. The question is if other problems pop up when you try to do it at that scale.
Possible but it's not really a good plan for performance.
You will make IF connection between the 4 parts that you then cut.
but this means EPYC ends up in exactly the same numa situation like it is now. So no it's one big die with connections to all mem channels from every core without having to jump to other parts of the die via IF to get to the right memory channel.
Possible but it's not really a good plan for performance.
You will make IF connection between the 4 parts that you then cut.
but this means EPYC ends up in exactly the same numa situation like it is now. So no it's one big die with connections to all mem channels from every core without having to jump to other parts of the die via IF to get to the right memory channel.
If it's the same numa situation that's not a bad thing. I don't think that's a problem with server/data center applications because they've been dealing with multisocket solutions for years. If anything keeping the same numa model would be good because of continuity and compatibility.
Adoredtv:s leak never mentioned a I/O die, it was just speculation from adored himself. And it always been obvious why, it adds latency and that kills gaming performance.
I think it Zen2 will be similiar to Threadripper, 2 dies with 8 cores sewed into a total package. That's why we should not be excited, the gaming performance will probably be meh like ryzen 1xxx series was.
The cpu+gpu combo will still be an APU/SOC I think.
Yes I know that masks themselves may not be that expensive but I mean total developmental cost of the new die with, as you say, the ported ddr4 controllers and what not. Laying out the circuits and validating the whole design will also take time and money.
Rome I/O die (~420mm²) already has (improved?) DDR4 PHYs, PCIe 4.0, and other IO that could be used for a smaller 14nm IO die. Only in the case that Rome IO die would use 14HP instead of 14LPP, it would make things much more complicated. Current Zeppelin and Raven Ridge also has a lot of working reusable IP on them so 14nm (or 12nm) would make the most sense for a small IO die without any CPU cores.
It only makes sense for AMD to do that if they can expect to sell enough chips to spread the cost and still make a profit.
If AMD spends 100 million developing the new die but can only sell 1 million chips, then the total cost of each chip is 100$ plus whatever it cost to manufacture it.
My point is the cost of each wafer is a fraction of what it took to design the chip and looking at yields and manufacturing cost tells us almost nothing without knowing how much it cost to develop the chip, or how many units AMD expects to sell.
That's exactly why it made so much sense for many of us that AMD would have went with one or two chiplets (7nm) and one small IO die (14nm) design. It still seems like the most cost effective solution (from both design and silicon cost standpoint) that would have good opportunities for die salvage and binning from a large pool of small ~72mm² chiplets.
I was only trying to make sense what the newest AdoredTV video is suggesting.
Still we should not take these leaks and rumors as facts and hopefully by CES 2019 we are much wiser. So we really don't know for sure whatever design Ryzen 3k will use, what the prices or clock speeds will be and what are the core counts for different SKUs. It's fun to speculate but looking at current Ryzen, it's pretty clear that AMD has a good plan (also for desktop) even if we don't yet know what it will be.
We all know that Rome looks extremely promising and most of us would likely agree that Intel knows that AMD is going to take the performance lead for a while at least in server space. The most important thing for AMD would be to gain more server market share and more profits from there. They are already doing very well on desktop and that's not going to change for a while. Still they need more market share in each segment while they have the process lead.
Adoredtv:s leak never mentioned a I/O die, it was just speculation from adored himself. And it always been obvious why, it adds latency and that kills gaming performance.
It's adds some latency for sure but we can't really state that it would kill gaming performance. There's likely 32MB of L3 cache for each chiplet and that would certainly benefit games. Zen 2 also has better prefetchers and that also helps to feed the cores regardless of what design they chose to go with. IPC for Zen2 will go up but we just don't yet know by how much.
I think it Zen2 will be similiar to Threadripper, 2 dies with 8 cores sewed into a total package. That's why we should not be excited, the gaming performance will probably be meh like ryzen 1xxx series was.
Ryzen was a new CPU architecture so it took time for game developers to get to know it. Zen 2 will very likely be used in both PS5 and the next XB so that would only benefit AMD on the PC gaming platform also. I think we should be excited for AMD's 7nm x86 parts (and Navi also for the GPU front) because that's the biggest thing in PC market in 2019.
Would a 72mm² chiplet be able contain 8 cores, 2xDDR4 memory controllers, 24-32xPCIe4 and alll other IO? Seems like the chiplet is too small to have all that. Let's hope that we get clearer info a little bit later.
I'm going with 16c for Ryzen 3xxx so two chiplets which have 1x DDR4 IMC and 12x PCIe4 lanes each, plus the interface for direct communication. Sure a close call.
Dr. Su talked about Zen 2 being a system architecture change whereas the above guess would essentially make it a Zeppelin MCM update on 7nm. Imo not likely, we will see.
I'm going with 16c for Ryzen 3xxx so two chiplets which have 1x DDR4 IMC and 12x PCIe4 lanes each, plus the interface for direct communication. Sure a close call.
Dr. Su talked about Zen 2 being a system architecture change whereas the above guess would essentially make it a Zeppelin MCM update on 7nm. Imo not likely, we will see.
What about 6C models then? Would they have just one DDR4 IMC or would they have two dies each? That would be a lot of 7nm silicon for a $100 SKU even if most of it would be salvaged dies. They would also have to separate dual DD4 memory controllers which they haven't done previously (sure their dual DDR4 controller also works in single channel mode). Your suggestion would still have an IF-fabric link (IFOP2.0) between dies so memory latency would be bifurcated. I would rather go with two chiplets and one IO die instead but sure, your design would have at least one local memory channel for each die. Having two memory controllers on die would allow just to use one die for 6C and 8C models. 12C and 16C models would be bifurcated, though.
Edit: I should have read more carefully what you had stated. That's a very bold assumption for a 72mm² chiplet to have 8 cores, 32MB of L3 cache, 1xDDR4 PHY, 12 PCIe, 2xUSB, etc. Maybe you could remove half of the L3 cache (16MB/chiplet) but that would hurt Rome's IO die + 8 chiplets design based performance likely a lot. Lisa Su has stated that IO doesn't scale that well for 7nm so there's not that much room in that small chiplet. Maybe it's time for AdoredTV to inquire his sources and get some clearer information on some things. Maybe there's still a change of 14nm small IO die.
If we're assuming that there actually is a Navi GPU chiplet (or Navi main die) then there would be (at least) two possible designs (keeping all previous recent assumptions):
With a small ~72mm² Navi-chiplet
With a larger (~120 mm²) Navi GPU die
Both designs have pros and cons but both would also add to the developing costs of Ryzen 3000 desktop chips. Small Navi-chiplet would have better yields but larger Navi GPU die would have more control over main memory accesses as it would also contain DDR4 memory controllers. I'm too tired to think this anymore and will just leave this here. Please listen and see carefully what AdoredTV had to say and make your own assumptions based on that.
I suggest to keep an open mind for many different possibilities that Ryzen 3000 could be. Since AdoreTV's new video, everything got much less clear all of a sudden. But it's okay and after CES 2019 we shoud know at least a little bit more.
If you have any other suggestions, please share them with us.
That would be best for a console APU. Like having a Navi 10 with a IF link and 256bit gddr6 and then the CPU chiplet is attached directly to the navi and running on navi memory whiout using a i/o die.
Latency would be crap but still a hell of a lot faster than ps4.
Navi probably has a builtin USB controller un order to provide USB c vídeo out. This could be used on a console to provide USB support. And the CPU Cores provide the pcie if needed.
You would need a external sata chip but those are cheap.
That would be best for a console APU. Like having a Navi 10 with a IF link and 256bit gddr6 and then the CPU chiplet is attached directly to the navi and running on navi memory whiout using a i/o die.
Thats's also what I thought. If the consoles would not use a monolithic die or a separate 14nm IO die then sure using one standard Rome CPU chiplet and a larger Navi part with GDDR6 controllers on die would be a good choice. That would allow AMD to use those avarage or below avarage Rome chiplets for consoles also. As you stated the design would be very similar to speculative Ryzen 3k one only with a larger Navi part with GDDR6 MCs.
32MB cache is a lot and general latency would be actually very good and much better than what current consoles have. Keep in mind than Zen 2 has improvements for prefetchers also and game developers can really optimize for a specific architecture. Therefore some additional latency shouldn't be that big of problem especially for PS5/next XB. We still don't know how it would affect gaming performance on PCs eithers.
Now for desktop. the already existing SBs can provide general i/o (sata, USB, etc) needed, you dont need a Navi chiplet for that, but you DO need to have the DDR4 controller SOMEWHERE. And i dont think it will be on the CPU since i dont see AMD producing more than 1 CPU chiplet. Maybe they added a single DDR4 controller on the cpu chiplet. And they are going for all dual chiplets.
The mayor problem i see from this? this is going to cause compatibility problems on existing motherboards the current gen Ryzen are 100% SOC and lossing some of the integrated I/O like the Sata controller is going to cause problems on some mbs.
I really dont see then adding general i/o to the Navi or the cpu chiplets, is not needed.
So im still on the idea that there is just one 7nm CPU chiplet for everything and 3 7nm Navis also for everything, the Navi 12, Navi 10 and Navi 20 whiout special GPU chiplets.
Lets think:
-7nm 8C CPU chiplet with single DDR4 controller, PCI-E and IF link
-Navi 12 64bits DDR4, 128/256bit GDDR5, IF Link, USB 3.1.
-Navi 10 256bit GDDR6, IF Link, USB 3.1
-Navi 20 ...
Desktop:
-2 CPU chiplets for 6C up to 16C CPU-only options, Dual channel DDR4, General I/O on SB.
-Picasso APU provides monolithic 4C Zen 1 APUs until Zen 2 APU arrives.
-Navi 12 APU from 4 to 8C with dual channel DDR4 (1 Navi 12 + 1 CPU chiplet)
Consoles:
-1 CPU chiplet + 1 Navi chiplet, cpu provides PCI-E lanes for add-ons, Navi provides USB support, no sata support, but you can use any cheap 3rd party option attached to the pci-e.
Notebook Zen 2 APU:
-1 CPU + 1 Navi 12, dual channel DDR4, with optional GDDR5 to give dGPU performance.
Now for desktop. the already existing SBs can provide general i/o (sata, USB, etc) needed, you dont need a Navi chiplet for that, but you DO need to have the DDR4 controller SOMEWHERE. And i dont think it will be on the CPU since i dont see AMD producing more than 1 CPU chiplet. Maybe they added a single DDR4 controller on the cpu chiplet. And they are going for all dual chiplets.
The mayor problem i see from this? this is going to cause compatibility problems on existing motherboards the current gen Ryzen are 100% SOC and lossing some of the integrated I/O like the Sata controller is going to cause problems on some mbs.
I really dont see then adding general i/o to the Navi or the cpu chiplets, is not needed.
So im still on the idea that there is just one 7nm CPU chiplet for everything and 3 7nm Navis also for everything, the Navi 12, Navi 10 and Navi 20 whiout special GPU chiplets.
Lets think:
-7nm 8C CPU chiplet with single DDR4 controller, PCI-E and IF link
-Navi 12 64bits DDR4, 128/256bit GDDR5, IF Link, USB 3.1.
-Navi 10 256bit GDDR6, IF Link, USB 3.1
-Navi 20 ...
I don't think dual chiplets with each one having a single ddr4 controller is what's going to happen if the rumors of there being a 6 core ryzen are true. With 4 ccxs, the cores will have to be disabled in quads.
From my perspective, adoredTVs latest information is kind of contradictory to his previous one. I can't imagine it's worth it for AMD to produce a separate 7nm die for the consumer space. If they're not using an IO die then I'm out of ideas on what they're gonna do.
Edit: Here's an idea: what if they do one 14nm zen+ die and a 7nm zen2 die connected with IF? completely unseen before as adoredTV says.
I don't think dual chiplets with each one having a single ddr4 controller is what's going to happen if the rumors of there being a 6 core ryzen are true. With 4 ccxs, the cores will have to be disabled in quads.
From my perspective, adoredTVs latest information is kind of contradictory to his previous one. I can't imagine it's worth it for AMD to produce a separate 7nm die for the consumer space. If they're not using an IO die then I'm out of ideas on what they're gonna do.
As far as i know the only requeriments is having equal amount of enabled cores on each. We dont know the internal structure of a CPU chiplet, it may be a single CCX. If so a 6C is possible. But probably not a $100. ANd that makes sence.
The whole point of the chiplet design was to be highly versatile. That would mean that a 72nm² chiplet would only contain features that are needed for all use cases including 8 cores, 32MB L3 cache and an IF link to connect to an IO die (or some other (main) die). We have already calculated that there's not much room for anything else. If AMD would have been able to add a single DDR4 controller to each chiplet then that design would still have that IF-link between dies and would not solve the so called latency issues that we're speculating on and have no actual information about. I think that Rome chiplets are pure in the sense that they do not have overlapping features and AMD has just added more L3 cache (compared to Zen1) which sound like a good plan.
I think that AdoredTV should do some more digging and post another video with some more concrete and less vague information. A few questions that he should ask from his sources could be these:
How many dies (chiplets) does Ryzen 3000 contain? Two or three?
How can you tell that all chiplets are only 7nm? You sure can't tell just by looking at Rome that one die is 14nm and 8 others are 7nm.
As far as i know the only requeriments is having equal amount of enabled cores on each. We dont know the internal structure of a CPU chiplet, it may be a single CCX. If so a 6C is possible. But probably not a $100. ANd that makes sence.
I can guarantee and will wager a significant amount of money that each ccx is still 4 cores unless they changed the topology to a ring bus or mesh network (they probably haven't because it doesn't scale well). That is why a 6 core CPU with 2 dies is impossible unless its possible to disable an entire ccx.
The whole point of the chiplet design was to be highly versatile. That would mean that a 72nm² chiplet would only contain features that are needed for all use cases including 8 cores, 32MB L3 cache and an IF link to connect to an IO die (or some other (main) die). We have already calculated that there's not much room for anything else. If AMD would have been able to add a single DDR4 controller to each chiplet then that design would still have that IF-link between dies and would not solve the so called latency issues that we're speculating on and have no actual information about. I think that Rome chiplets are pure in the sense that they do not have overlapping features and AMD has just added more L3 cache (compared to Zen1) which sound like a good plan.
I think that AdoredTV should do some more digging and post another video with some more concrete and less vague information. A few questions that he should ask from his sources could be these:
How many dies (chiplets) does Ryzen 3000 contain? Two or three?
How can you tell that all chiplets are only 7nm? You sure can't tell just by looking at Rome that one die is 14nm and 8 others are 7nm.
In my post in the previous page, I listed the reasons why I believe Ryzen 3k will be two dies or three dies depending on which tier it is.
In AMD's Next Horizon's event, they said that it was 8 7nm chiplets plus a 14nm IO Die.
I don't know about Adored's latest video. I don't see why AMD would go monolithic with consumer and chiplets for enterprise. Granted the monolithic might just be for pure speed, but an IF link to an IO die should be faster than current Ryzen chips. It solves a bunch of issues. Chiplets make high investments in node technology pay off sooner. Adored mentions packaging and shipping for a reason, but the chips are already being made in one place and packaged in another. Container transport via ship is cheap. It's around $5000 for a 40ft as a one off. You can put A LOT of chips in a 40ft container. I just can't see why AMD wouldn't go for the most cost effective/profit generating choice. If anything it's something that no one understands yet.
That wasn't the point. If you would get a Rome CPU on your hands with no previous knowledge what it contains, you could guess that the IO die is using a different process than the smaller dies but just by looking at it, you have no way to know for sure. You could make educated guesses based on size but that's about it.
If AdoredTV's source has seen what Ryzen 3000 with 3 small dies looks like he/she could have assumed that all of them are so small that they must be 7nm. Still the IO die could be 14nm even if it's about the same size as the other chiplets. There's room for a lot of misinterpretation for these leaks where someone saw something. Even if one of his sources says that Ryzen 3000 will be all 7nm that's not a fact and there still could be a 14nm small IO die. AdoredTV should also get a second source for his Ryzen 3000 will only be 7nm rumor.
If there is no (14nm) IO die for desktop then I'm still assuming what i did previously that it's a monolithic 8C die with one IF-link to connect to one Rome chiplet (12C and 16C models only).
That wasn't the point. If you would get a Rome CPU on your hands with no previous knowledge what it contains, you could guess that the IO die is using a different process than the smaller dies but just by looking at it, you have no way to know for sure. You could make educated guesses based on size but that's about it.
If AdoredTV's source has seen what Ryzen 3000 with 3 small dies looks like he/she could have assumed that all of them are so small that they must be 7nm. Still the IO die could be 14nm even if it's about the same size as the chiplets. There's room for a lot of misinterpretation for these leaks where someone saw something. Even if one of his sources says that Ryzen 3000 will be all 7nm that's not a fact and there still could be a 14nm small IO die. AdoredTV should also get a second source for his Ryzen 3000 will only be 7nm rumor.
If there is no (14nm) IO die for desktop then I'm still assuming what i did previously that it's a monolithic 8C die with one IF-link to connect to one Rome chiplet (12C and 16C models only).
I don't doubt you because I was looking into that when I was trying to confirm that cores in each CCX correspond with each other, but I couldn't find any (or missed the) source that said an entire CCX could be disabled while leaving the other one on the die operable. Can you point me in the right direction please?
The whole point of the chiplet design was to be highly versatile. That would mean that a 72nm² chiplet would only contain features that are needed for all use cases including 8 cores, 32MB L3 cache and an IF link to connect to an IO die (or some other (main) die). We have already calculated that there's not much room for anything else. If AMD would have been able to add a single DDR4 controller to each chiplet then that design would still have that IF-link between dies and would not solve the so called latency issues that we're speculating on and have no actual information about. I think that Rome chiplets are pure in the sense that they do not have overlapping features and AMD has just added more L3 cache (compared to Zen1) which sound like a good plan.
I think that AdoredTV should do some more digging and post another video with some more concrete and less vague information. A few questions that he should ask from his sources could be these:
How many dies (chiplets) does Ryzen 3000 contain? Two or three?
How can you tell that all chiplets are only 7nm? You sure can't tell just by looking at Rome that one die is 14nm and 8 others are 7nm.
Whiout an I/O die thats the only option, unless there is a smaller Navi that we dont know of with only dual channel DDR4 and all Ryzen chips launch with that, but that by itselft it is a I/O die, IN FACT, it is the "ye olde" Northbridge.
But that would be creating a chip, an NB chip, that is only for desktops and mobile. i really dont think AMD is going to do that.
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