Speculation: Ryzen 3000 series

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What will Ryzen 3000 for AM4 look like?


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amd6502

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Apr 21, 2017
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imho, Matisse is purely a CPU-orienated chiplet design. It has no GPU functionality whatsoever. Renoir doesn't use chiplets whatsoever. It is a fully integrated N7 design.

Renoir should have the same CPU/GPU CU count as Picasso/Raven Ridge; 4x Zen2/11x Vega2. However, there might be more significant changes in the PSP, VCN, and IMC.

With only a small amount of transistors added (~65mm2?) to the consumer IO hub, they could add Vega 3, and it would be a very good added feature as well as allow them to enter power user laptop in the 25W-45W cTDP with Matisse being able to come in the form of an 8c/16t mobile APU. (This would be like the threatripper of the notebook world). Isn't it still too early to tell wether a basic iGPU is there yet?

If you take RR's 210mm2 die, and subtract the CPU CCX and the Vega units (althogether ~120mm2) you get 90mm2 of uncore for the APU. The consumer IO hub is about 123mm2, so this leaves ~33mm2 for a few units of Vega as well as control logic and IF to drive a single 7nm chiplet and extra pcie lanes.

I think your guess on Renoir sounds pretty good. 4c/8t is still a sweet spot for mobile and the majority of the desktop world. IMHO it would be kind of sad though, if Navi didn't make it into that APU.
 
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maddie

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With only a small amount of transistors added (~65mm2?) to the consumer IO hub, they could add Vega 3, and it would be a very good added feature as well as allow them to enter power user laptop in the 25W-45W cTDP with Matisse being able to come in the form of an 8c/16t mobile APU. (This would be like the threatripper of the notebook world). Isn't it still too early to tell wether a basic iGPU is there yet?

I think your guess on Renoir sounds pretty good. 4c/8t is still a sweet spot for mobile and the majority of the desktop world. IMHO it would be kind of sad though, if Navi didn't make it into that APU.
For the earlier Zen iterations, chiplets led to high idle power (fabric). Unless fixed, definitely not suitable for mobile.
 

Topweasel

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Oct 19, 2000
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With only a small amount of transistors added (~65mm2?) to the consumer IO hub, they could add Vega 3, and it would be a very good added feature as well as allow them to enter power user laptop in the 25W-45W cTDP with Matisse being able to come in the form of an 8c/16t mobile APU. (This would be like the threatripper of the notebook world). Isn't it still too early to tell wether a basic iGPU is there yet?

If you take RR's 210mm2 die, and subtract the CPU CCX and the Vega units (althogether ~120mm2) you get 90mm2 of uncore for the APU. The consumer IO hub is about 123mm2, so this leaves ~33mm2 for a few units of Vega as well as control logic and IF to drive a single 7nm chiplet and extra pcie lanes.

I think your guess on Renoir sounds pretty good. 4c/8t is still a sweet spot for mobile and the majority of the desktop world. IMHO it would be kind of sad though, if Navi didn't make it into that APU.

There is no basic APU. An APU due to design choices with AM4 means an immediate loss of PCIe lanes with the potential of more on a CPU AMD already sacrificed PCIe lanes to keep it on a ZIF socket instead of LGA socket while supporting APU's and standard CPU's. Any APU AMD makes for AM4 will be either a full blown APU, or a Full Blown CPU. Nothing in between.
 

Topweasel

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Any predictions on the balancing of CPU to the stability of the memory while overclocking?

I would assume that this going to be mostly a fixed thing. Don't know if that's good or bad (like early Ryzen 1st gen CPU's tended to clock memory better when the CPU as whole is overclocked). But now with the IO chip, I suspect the memory controller and it's performance is going to be completely divorced from any work we do on overclocking the cores.
 
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amd6502

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Apr 21, 2017
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There is no basic APU. An APU due to design choices with AM4 means an immediate loss of PCIe lanes with the potential of more on a CPU AMD already sacrificed PCIe lanes to keep it on a ZIF socket instead of LGA socket while supporting APU's and standard CPU's. Any APU AMD makes for AM4 will be either a full blown APU, or a Full Blown CPU. Nothing in between.

With so few compute units in Vega 3, how many PCIe lanes must be lost? a full 8? Also, I wasn't talking about a regular mobile but a power user mobile ~35W+ that might also go into very specialty laptops and high end all in ones. For gaming or niche laptops, battery life isn't always top importance, and I think they can get the idle wattage low enough, even with the off chiplet memory controller.
 

Topweasel

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Oct 19, 2000
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With so few compute units in Vega 3, how many PCIe lanes must be lost? a full 8? Also, I wasn't talking about a regular mobile but a power user mobile ~35W+ that might also go into very specialty laptops and high end all in ones. For gaming or niche laptops, battery life isn't always top importance, and I think they can get the idle wattage low enough, even with the off chiplet memory controller.

This has nothing to do with transistors on the CPU or power usage. It's about pin outs. To fit VGA functionality on the socket AMD already dropped 8 PCIe lanes from Ryzen (supports 32 lanes, but only can use 24 of them). The APU's then lose another 8 lanes, to actually add the functionality. There is some debate on why that is. But the point remains that adding Video output support on socket has already cost Ryzen, adding it to the chips themselves might cost more. Until we get a new socket (probably LGA) I don't think simple igpu's can be a thing. But power and cost don't seem like an actual reasonable reason for business desktops not to use Ryzen so I don't think there really is as much of an impetus to add it anyways. I personally don't think this is a reasonable request.
 

tomatosummit

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Mar 21, 2019
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This has nothing to do with transistors on the CPU or power usage. It's about pin outs.

Unless AM4 specifically stops >16pcie lanes being in use with the video outputs then you're right. I don't think there's any particular switching going on and the socket should support all 24 lanes and video at the same time. Raven Ridge just doesn't have more than 16lanes on the die.
The i/o die will certainly have transistor concerns but it can be made to the am4 spec unlike zeppelin that wastes loads of IO when used in ryzen. So it needs it's memory controllers, 24pcie lanes, the new IF links, 4USB3 lanes and loses the four old IF lanes, various gpio functions (socket interconnect for example), maybe the 10gbe (expect to keep a couple of them for future embedded parts) . I think the ~120mm^2 io die is a bit large without using that space on something new which I hope is a token Igpu but as someone else has mentioned the amount of fixed function gpu parts is quite large.
 

Topweasel

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Oct 19, 2000
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Unless AM4 specifically stops >16pcie lanes being in use with the video outputs then you're right. I don't think there's any particular switching going on and the socket should support all 24 lanes and video at the same time. Raven Ridge just doesn't have more than 16lanes on the die.

I don't know I think there is more to it. Might be that the die doesn't include it because there is switching and they would lose those ports anyways. Personally I think people are just putting to much hope into this, where I don't see this really affecting design wins for AMD.
 

Gideon

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Nov 27, 2007
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Cosidering how every possible Vega GPU has also leaked in linux drivers, I would assume we would already have some leaks about Matisse GPU as well. Which seems to indicate that there probably isn't a GPU
 

cortexa99

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Gideon

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More info from "1usmus": techpowerup

Looks like the Infinity Fabric multiplier is actually to make it slower :( (but this at least hints at memory clocked higher than 4GHz):
When doing serious memory overclocking, it can happen that the Infinity Fabric can't handle the increased memory speed. Remember, Infinity Fabric runs at a frequency synchronized to memory. For example, with DDR-3200 memory (which runs at 1600 MHz), Infinity Fabric will operate at 1600 MHz. This is the default of Zen, Zen+ and also Zen 2. Unlike earlier generations, the new BIOS offers UCLK options for "Auto", "UCLK==MEMCLK" and "UCLK==MEMCLK/2". The last option is new and will come in handy when overclocking your memory, to achieve stability, but at the cost of some Infinity Fabric bandwidth.
 
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Thunder 57

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More info from "1usmus": techpowerup

Looks like the Infinity Fabric multiplier is actually to make it slower:( (but this at least hints at memory clocked higher than 4GHz):

If this is accurate, it looks like we are still dealing with 4 core CCX's. I was hoping for the chiplet to be its own CCX. That would be more costly though. Or was all of this already known and I just missed it?
 

beginner99

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Jun 2, 2009
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Or was all of this already known and I just missed it?

Wasn't known but suspected because 4-core ccx makes sense because it's simple connecting these 4 cores together.

But i have to admit it's disappointing to see IF still coupled to memory plus the fact that IF itself seems to be clock limited. Doesn't bode well for latency.
 

Kedas

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Dec 6, 2018
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More info from "1usmus": techpowerup

Looks like the Infinity Fabric multiplier is actually to make it slower:( (but this at least hints at memory clocked higher than 4GHz):
They doubled the IF BW so I assume 'half' is the same as what we have in Zen1
or they doubled the number of IF lanes, anyway half the IF speed should be the same like what you have now.
 
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amd6502

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Cosidering how every possible Vega GPU has also leaked in linux drivers, I would assume we would already have some leaks about Matisse GPU as well. Which seems to indicate that there probably isn't a GPU

As far as GPU related kernel changes, would linux as it is already not recognize the iGPU?

I somewhat agree it's almost a long shot, but isn't Vega 3 already well built into the linux kernel? Also, we haven't really seen linux leaks related to the CPU portion either.

So gotta be patient but I think good chance we in the next month or so maybe start seeing linux leaks related to 7nm CPU. May1 is the big anniversary, and I think hopefully they wil be far along then that they can announce part of the product release. (Then if lucky expect availability sometime June?)


Memory latency is better on new platform(X570?) but worse on old one(X370,X470).
Stay tuned.:rolleyes:
https://translate.google.com/translate?hl=en&sl=auto&tl=en&u=https://www.chiphell.com/thread-1974190-1-2.html

So at this point it does look like the IO die might possibly be able to support two chiplets. (Makes sense because this enables Ryzen 9 which could be well needed). Maybe on these newer boards there is a cache/buffer chip between the socket (memory controller) and the RAM ; I speculate this is used when the IO hub drives more than one chiplet. I imagine (speculate) the io hub itself has some sort of L4 like buffer, but its first duty would be store data about all L3 values that exist redundantly from one chiplet to the other, and guarantee cache coherency between the two chiplets. Any remaining space is used as L4 (LLC). An onboard L4 built into the mobo could relieve resources and let the IO hub's cache dedicate itself to the primary task.

Whether current boards support any 2 chiplet models is another interesting question.
 
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DrMrLordX

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Apr 27, 2000
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@Gideon

I've been reading that techpowerup article you pasted, and one item jumped out at me:

The I/O controller die has 100 GB/s IFOP links to each of the two 8-core chiplets, and another 100 GB/s IFOP link connects the two chiplets to each other.

That's good news for reducing chiplet-to-chiplet latency. I'm a bit concerned about how that will affect IF power usage on Rome, though. Rome may use a different IF topology.
 

Caveman

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Nov 18, 1999
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Since this is called the "speculation" thread for Ryzen 3000, can anyone cut to the chase and estimate when it's going to hit the market and if it will be faster than the 9900 series Intel CPUs? Is this the start of a new architecture that can lead the way to the next generation?
 
Feb 4, 2009
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Since this is called the "speculation" thread for Ryzen 3000, can anyone cut to the chase and estimate when it's going to hit the market and if it will be faster than the 9900 series Intel CPUs? Is this the start of a new architecture that can lead the way to the next generation?

Likely July
Likely be close to 9900
 

Kedas

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Dec 6, 2018
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There will be extra speed due to the IF between the 2 core dies, doesn't transport DDR4 data.
It will also be interesting to know if this link stays at 100GB/s when you reduce the speed by 2 so you get 2 time 50GB/s and 1 time 100GB/s.

I also made this image below to show the similarity with a 'crippled' 16 core threadripper 2000.
 

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