It was already released bios/AGESA saying about compatibility with upcoming processors with the AGESA number 0070
imho, Matisse is purely a CPU-orienated chiplet design. It has no GPU functionality whatsoever. Renoir doesn't use chiplets whatsoever. It is a fully integrated N7 design.
Renoir should have the same CPU/GPU CU count as Picasso/Raven Ridge; 4x Zen2/11x Vega2. However, there might be more significant changes in the PSP, VCN, and IMC.
For the earlier Zen iterations, chiplets led to high idle power (fabric). Unless fixed, definitely not suitable for mobile.With only a small amount of transistors added (~65mm2?) to the consumer IO hub, they could add Vega 3, and it would be a very good added feature as well as allow them to enter power user laptop in the 25W-45W cTDP with Matisse being able to come in the form of an 8c/16t mobile APU. (This would be like the threatripper of the notebook world). Isn't it still too early to tell wether a basic iGPU is there yet?
I think your guess on Renoir sounds pretty good. 4c/8t is still a sweet spot for mobile and the majority of the desktop world. IMHO it would be kind of sad though, if Navi didn't make it into that APU.
With only a small amount of transistors added (~65mm2?) to the consumer IO hub, they could add Vega 3, and it would be a very good added feature as well as allow them to enter power user laptop in the 25W-45W cTDP with Matisse being able to come in the form of an 8c/16t mobile APU. (This would be like the threatripper of the notebook world). Isn't it still too early to tell wether a basic iGPU is there yet?
If you take RR's 210mm2 die, and subtract the CPU CCX and the Vega units (althogether ~120mm2) you get 90mm2 of uncore for the APU. The consumer IO hub is about 123mm2, so this leaves ~33mm2 for a few units of Vega as well as control logic and IF to drive a single 7nm chiplet and extra pcie lanes.
I think your guess on Renoir sounds pretty good. 4c/8t is still a sweet spot for mobile and the majority of the desktop world. IMHO it would be kind of sad though, if Navi didn't make it into that APU.
Any predictions on the balancing of CPU to the stability of the memory while overclocking?
There is no basic APU. An APU due to design choices with AM4 means an immediate loss of PCIe lanes with the potential of more on a CPU AMD already sacrificed PCIe lanes to keep it on a ZIF socket instead of LGA socket while supporting APU's and standard CPU's. Any APU AMD makes for AM4 will be either a full blown APU, or a Full Blown CPU. Nothing in between.
With so few compute units in Vega 3, how many PCIe lanes must be lost? a full 8? Also, I wasn't talking about a regular mobile but a power user mobile ~35W+ that might also go into very specialty laptops and high end all in ones. For gaming or niche laptops, battery life isn't always top importance, and I think they can get the idle wattage low enough, even with the off chiplet memory controller.
This has nothing to do with transistors on the CPU or power usage. It's about pin outs.
Unless AM4 specifically stops >16pcie lanes being in use with the video outputs then you're right. I don't think there's any particular switching going on and the socket should support all 24 lanes and video at the same time. Raven Ridge just doesn't have more than 16lanes on the die.
When doing serious memory overclocking, it can happen that the Infinity Fabric can't handle the increased memory speed. Remember, Infinity Fabric runs at a frequency synchronized to memory. For example, with DDR-3200 memory (which runs at 1600 MHz), Infinity Fabric will operate at 1600 MHz. This is the default of Zen, Zen+ and also Zen 2. Unlike earlier generations, the new BIOS offers UCLK options for "Auto", "UCLK==MEMCLK" and "UCLK==MEMCLK/2". The last option is new and will come in handy when overclocking your memory, to achieve stability, but at the cost of some Infinity Fabric bandwidth.
More info from "1usmus": techpowerup
Looks like the Infinity Fabric multiplier is actually to make it slower (but this at least hints at memory clocked higher than 4GHz):
Or was all of this already known and I just missed it?
Why?But i have to admit it's disappointing to see IF still coupled to memory
The opposite, for inserting more clock domains always results in more latency.Doesn't bode well for latency.
They doubled the IF BW so I assume 'half' is the same as what we have in Zen1More info from "1usmus": techpowerup
Looks like the Infinity Fabric multiplier is actually to make it slower (but this at least hints at memory clocked higher than 4GHz):
Cosidering how every possible Vega GPU has also leaked in linux drivers, I would assume we would already have some leaks about Matisse GPU as well. Which seems to indicate that there probably isn't a GPU
Memory latency is better on new platform(X570?) but worse on old one(X370,X470).
Stay tuned.
https://translate.google.com/translate?hl=en&sl=auto&tl=en&u=https://www.chiphell.com/thread-1974190-1-2.html
The I/O controller die has 100 GB/s IFOP links to each of the two 8-core chiplets, and another 100 GB/s IFOP link connects the two chiplets to each other.
Since this is called the "speculation" thread for Ryzen 3000, can anyone cut to the chase and estimate when it's going to hit the market and if it will be faster than the 9900 series Intel CPUs? Is this the start of a new architecture that can lead the way to the next generation?