Question Speculation: RDNA3 + CDNA2 Architectures Thread

[uzzi38]

Man I have been dying to make this one for a while now.

First rumours for RDNA3 are here so new thread time!

Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3 is much bigger than from RDNA1 to RDNA2. We should expect many big improvements in GFX11. 🤔" / Twitter

 

[uzzi38]

Yes, but he probably means that Nvidia has more to gain (going from Samsung’s 8nm to N5) than AMD does.

That's what people said about RDNA2 vs Ampere too.

Lets just wait and see what happens. We'll know for sure where AMD and Nvidia stand in time.

 

[uzzi38]

If the slide is real RDNA3 will release only in 2023. And if Nvidia launching ADA in july rumor is true I preditc that AMD will reach ~5% market share by the time RDNA3 launches.

What slide? Also lmfao at the 5% comment.

 

[uzzi38]

Can we draw a conclusion from the slide bellow that top RDNA3 sku (7950XT ???) will have same TBP of 335W as RX6950XT ???

Oh right this one. Yeah no, it's probably BS.

 

[soresu]

It has been like Q4 for a Zen4 launch quite some time, then we were down to mid September and now we are at a point where Gigabyte and all the others will showcase their X670 boards already during the next week. That means probably that it's even earlier than September.

Tha goes by the assumption that AMD will follow the precedent of the last 2 launch cycles to announced the new Zen and RDNA architectures at the same time.

Given the higher prevalence of Zen4 talk from AMD vs RDNA3 talk I think it's definitely possible that CPU and GPU announcements could be decoupled this time around.

We'll see either way tomorrow with the Computex keynote I guess.

 

[jpiniero]

Given that they just released the RDNA 2 Refresh a week and a half ago, it doesn't seem like the right time to talk about RDNA 3.

 

[Karnak]

Don't see the problem though.

July 2020 -> Zen2 refresh (XT's)
November 2020 -> Zen3

 

[linkgoron]

Given that they just released the RDNA 2 Refresh a week and a half ago, it doesn't seem like the right time to talk about RDNA 3.

AMD's refreshes these days exist, IMO, as a pre-release to make the next-gen look better. They increase the price, so that the next-gen price increase won't look so bad. This gives the the opportunity to say "look how much we've increased price/perf compared to the previous gen" and "same MSRP as previous gen" (or "just over") instead of anything else - same as the 3800XT was.

 

[biostud]

Seems like dual and triple x16 slots are the new black for AM5 motherboards. Is AMD telling us that CF is coming back in the future?

 

[uzzi38]

Oh right this one. Yeah no, it's probably BS.

The slide is definitely BS.

 

[Aapje]

Seems like dual and triple x16 slots are the new black for AM5 motherboards. Is AMD telling us that CF is coming back in the future?

My takeaway from the Computex presentation was more that there is going to be a lot of focus on DirectStorage for Radeon 7000 and that they want the entire AM5 platform to have PCIe 5 storage, even though low end motherboards will have PCIe 4 graphics slots.

This makes a lot of sense, since PCIe 4 is more than sufficient for even the fastest cards today, so unless they released low-end cards with too few lanes (Cough 6500 cough), lower end customers won't have a need for a PCIe 5 graphics slot for a long time.

 

[biostud]

My takeaway from the Computex presentation was more that there is going to be a lot of focus on DirectStorage for Radeon 7000 and that they want the entire AM5 platform to have PCIe 5 storage, even though low end motherboards will have PCIe 4 graphics slots.

This makes a lot of sense, since PCIe 4 is more than sufficient for even the fastest cards today, so unless they released low-end cards with too few lanes (Cough 6500 cough), lower end customers won't have a need for a PCIe 5 graphics slot for a long time.

Also that, I just thought the layout was weird in regards that 99.9% of users have one video card and then maybe one or two x1 cards.

 

[Timorous]

The slide is definitely BS.

What is BS about it? Lovelace is actually 900W TBP or N31 is going to be 450W TBP?

 

[moinmoin]

What is BS about it?

Putting a working title of an upcoming product name of the competition with a "rumored" disclaimer on a chart relating its supposed efficiency to your own unannounced upcoming product? Seems totally legit to me.

 

[Timorous]

Putting a working title of an upcoming product name of the competition with a "rumored" disclaimer on a chart relating its supposed efficiency to your own unannounced upcoming product? Seems totally legit to me.

Yea that is obvious. I was just wondering if Uzzi had some more specific info than the slide being BS.

 

[Mopetar]

Seems like dual and triple x16 slots are the new black for AM5 motherboards. Is AMD telling us that CF is coming back in the future?

I was wondering about that as well. If AMD is going to an MCM design that uses GPU chiplets then what makes it functionally different from SLI/Crossfire unless there's a "brain" chiplet that controls the others.

 

[fleshconsumed]

I was wondering about that as well. If AMD is going to an MCM design that uses GPU chiplets then what makes it functionally different from SLI/Crossfire unless there's a "brain" chiplet that controls the others.

Latency?

 

[uzzi38]

Yea that is obvious. I was just wondering if Uzzi had some more specific info than the slide being BS.

I know enough to say for certain that some people have been guessing out of their arses and it's an absolute joke.

A very not funny one.

 

[jpiniero]

I know enough to say for certain that some people have been guessing out of their arses and it's an absolute joke.

A very not funny one.

That's Youtubers for ya.

 

[Aapje]

What do you mean, the 7600 won't render 8k at 1 billion Hz?

 

[Frenetic Pony]

I was wondering about that as well. If AMD is going to an MCM design that uses GPU chiplets then what makes it functionally different from SLI/Crossfire unless there's a "brain" chiplet that controls the others.

So with MCM the work distribution, what lanes run what, is all still centrally controlled. There's one input stream to deal with, and all the figuring out of how to get that instruction stream and results and those results back to where they're needed, back and forth across chiplets is done on the hardware itself. Over what needs to be a very high bandwidth, very low latency, preferably very cheap connection (thus why it's taken so long to make).

The problem with "sli" and whatever is indeed latency, in part, and bandwidth. And the fact that there's two instruction streams going to two different chips who then may have to shuttle data back and forth to each other, requiring a lot of bandwidth and consideration of latency (and complication, lots of it) over PCIE (which might be saturated at points already), or everything has to be copied out twice to both cards, meaning a lot of the benefit is lost as you can't perfectly "split the screen in half" and have one card to one half and the other do the other half.Either way, you can pay double the cost for something that is not double the performance.

Meanwhile if you split a GPU in two each half costs less than one big whole, depending on the sizes as splitting a 200mm chip into 2 100mm chips you don't save much and it might even cost more as you end up needing extra hardware for that link between chiplets. But if you split a big enough chip, like a huge GPU or a 64 core CPU or etc. into two or more chiplets then even with some extra added hardware and etc. for chiplet cost your overall cost goes down.

 

[Stuka87]

So with MCM the work distribution, what lanes run what, is all still centrally controlled. There's one input stream to deal with, and all the figuring out of how to get that instruction stream and results and those results back to where they're needed, back and forth across chiplets is done on the hardware itself. Over what needs to be a very high bandwidth, very low latency, preferably very cheap connection (thus why it's taken so long to make).

The problem with "sli" and whatever is indeed latency, in part, and bandwidth. And the fact that there's two instruction streams going to two different chips who then may have to shuttle data back and forth to each other, requiring a lot of bandwidth and consideration of latency (and complication, lots of it) over PCIE (which might be saturated at points already), or everything has to be copied out twice to both cards, meaning a lot of the benefit is lost as you can't perfectly "split the screen in half" and have one card to one half and the other do the other half.Either way, you can pay double the cost for something that is not double the performance.

Meanwhile if you split a GPU in two each half costs less than one big whole, depending on the sizes as splitting a 200mm chip into 2 100mm chips you don't save much and it might even cost more as you end up needing extra hardware for that link between chiplets. But if you split a big enough chip, like a huge GPU or a 64 core CPU or etc. into two or more chiplets then even with some extra added hardware and etc. for chiplet cost your overall cost goes down.

AMD solved the bandwidth issue in the last iteration of Cross Fire. They did away with the bridge and used the PCIe bus, which solved the vast majority of issue. But then games all started to used deferred renderers which just don't work with Cross Fire or SLI.

Obviously we lack details on how AMD is going to handle chiplets. But I also highly doubt they would bank their entire future on a design where they don't deal with any of the basic things noted in your post.

 

[biostud]

AMD solved the bandwidth issue in the last iteration of Cross Fire. They did away with the bridge and used the PCIe bus, which solved the vast majority of issue. But then games all started to used deferred renderers which just don't work with Cross Fire or SLI.

Obviously we lack details on how AMD is going to handle chiplets. But I also highly doubt they would bank their entire future on a design where they don't deal with any of the basic things noted in your post.

Besides CF/SLI why could be the reason for so many x16/x8 boards only? I will have to use a Pcie5 x8 slot for my pcie3 x1 soundcard , and then be out of expansion slots. Weird.

 

[Stuka87]

Besides CF/SLI why could be the reason for so many x16/x8 boards only? I will have to use a Pcie5 x8 slot for my pcie3 x1 soundcard , and then be out of expansion slots. Weird.

To me this seems similar to when a new car comes out, so the automakers only show fully loaded versions of the car. Meaning we are seeing a lot of high end boards that have everything.

Or, it could mean that however AMD solved the issues around chiplet based GPUs, also solves the issue for CF. Making multi-GPUs a thing again.

However its worth noting that the announcement article for the X570 shows a board with a whole bunch of full length PCIe slots: https://www.anandtech.com/show/14406/amd-reveals-the-x570-chipset-pcie-4-is-here

 

[biostud]

To me this seems similar to when a new car comes out, so the automakers only show fully loaded versions of the car. Meaning we are seeing a lot of high end boards that have everything.

Or, it could mean that however AMD solved the issues around chiplet based GPUs, also solves the issue for CF. Making multi-GPUs a thing again.

However its worth noting that the announcement article for the X570 shows a board with a whole bunch of full length PCIe slots: https://www.anandtech.com/show/14406/amd-reveals-the-x570-chipset-pcie-4-is-here

The thing is it looks like a regression, as it is only two slots and nothing else. The X570 has several slots.

 

[Stuka87]

The thing is it looks like a regression, as it is only two slots and nothing else. The X570 has several slots.

Some have two, some have three.