Question Speculation: RDNA3 + CDNA2 Architectures Thread

[eek2121]

I think there is no cost advantage. AD103 is only 379 mm^2 of N5 related silicon and 4080 is not even using the full die. Navi 31’s GCD is 306 mm^2 of N5, along with 6 MCDs which are 37.5 mm^2 of N6. Add in its chiplet associated costs and higher VRAM amount and I think it’s clear there is no cost advantage for Navi 31.

The cost advantage would have materialized if Navi 31 was out of the 4080’s league in performance and closer to the 4090, against which it does have a massive cost advantage. Instead, it’s barely faster than the 4080 in rasterization and is well behind in RT performance. Still, AMD will be more than fine selling it at $1000 and it’s not a disaster like Vega, it’s just not better than Ada in that regard at all. If the performance was 25% higher like some are suggesting it should have been, then things would be different.

NVIDIA is using N4, which is similar, but not the same as N5. N4 is slightly more dense, but also a bit more expensive. NVIDIA also likely does not receive as large of a volume discount as AMD unless they pre-purchased a ton of capacity, which is doubtful. Remember AMD builds CPUs and other products at TSMC as well.

 

[eek2121]

Apparently, overclocking does help in certain titles, the overclocked XTX is nearly as fast as the 4090 in CP2077, for example: https://www.techpowerup.com/review/asus-radeon-rx-7900-xtx-tuf-oc/39.html

It will be interesting to see what happens in the future.

 

[Stuka87]

AMD is on a slight node backfoot, just like nVidia was last gen. The gap may be ever so slightly smaller, but it's there. And I don't exactly get what the point of pretending otherwise is.

We actually do not know this. RDNA3 is on N5, AD is on a modified N5 (called N4). Its similar to when AMD was on 16nm, and nVidia was on "12nm". It wasn't actually 12. Its just a naming change for a tweaked version of the mainline node.

Unless somebody finds out all the differences between N5 and N4, we won't know just what the differences are, or which one is better. But what we do know, is that N5 is cheaper, and likely more reliable (eg. better yields) because its used by everybody.

 

[guidryp]

We actually do not know this. RDNA3 is on N5, AD is on a modified N5 (called N4). Its similar to when AMD was on 16nm, and nVidia was on "12nm". It wasn't actually 12. Its just a naming change for a tweaked version of the mainline node.

Unless somebody finds out all the differences between N5 and N4, we won't know just what the differences are, or which one is better. But what we do know, is that N5 is cheaper, and likely more reliable (eg. better yields) because its used by everybody.

Yep, and NVidia is very fond of naming their own process, which is likely just an accumulation of tweaks that happen with any big customer as they design products, and nobody else bothers renaming their tweaks.

Their 12nm was called 12FFN, with the N being for NVidia, and it was essentially just NVidias tweak package on 16nm.

I think they are not using N4, but 4N, the special NVidia tweak package. I wouldn't expect it to be significantly different than what AMD is using.

 

[exquisitechar]

NVIDIA is using N4, which is similar, but not the same as N5. N4 is slightly more dense, but also a bit more expensive. NVIDIA also likely does not receive as large of a volume discount as AMD unless they pre-purchased a ton of capacity, which is doubtful. Remember AMD builds CPUs and other products at TSMC as well.

I don't even know if 4N is N4 or not, as I've seen conflicting reports. I don't think it makes a big difference, though.

 

[Kepler_L2]

NVIDIA is using N4, which is similar, but not the same as N5. N4 is slightly more dense, but also a bit more expensive. NVIDIA also likely does not receive as large of a volume discount as AMD unless they pre-purchased a ton of capacity, which is doubtful. Remember AMD builds CPUs and other products at TSMC as well.

Navi3x has higher density than Ada.

 

[Kaluan]

I don't even know if 4N is N4 or not, as I've seen conflicting reports. I don't think it makes a big difference, though.

It doesn't, but neither is it the same node. nVidia's is more advanced, wasn't there word that they pay more for it than AMD does for their? Ofc, that can be also up to AMD having perks from it's much better standing with TSMC.

But that was only half the point, the other is that 42% of Navi31 isn't even on "custom N5", but so called N6 (which bring no benefit over N7P non-logic wise AFAIK).
Last time I checked, SRAM density from ~N7 to ~N5 node was 1.3x and analog 1.2x
That's not "nothing".

BTW is AMD even using dense SRAM libraries on the MCDs? From a glance it doesn't seem so. No idea how much the 64bit memory interface takes up. So I may be totally off.

 

[Hitman928]

NVIDIA is using N4, which is similar, but not the same as N5. N4 is slightly more dense, but also a bit more expensive. NVIDIA also likely does not receive as large of a volume discount as AMD unless they pre-purchased a ton of capacity, which is doubtful. Remember AMD builds CPUs and other products at TSMC as well.

Nvidia did pre-purchase a ton of capacity. I don't know if it got them on equal pricing as AMD, but they bought a ton of capacity earlier in the year for their year end and early new year productions.

 

[Saylick]

Yep, and NVidia is very fond of naming their own process, which is likely just an accumulation of tweaks that happen with any big customer as they design products, and nobody else bothers renaming their tweaks.

Their 12nm was called 12FFN, with the N being for NVidia, and it was essentially just NVidias tweak package on 16nm.

I think they are not using N4, but 4N, the special NVidia tweak package. I wouldn't expect it to be significantly different than what AMD is using.

This. Nvidia marketing will market. You won't see a 4N node on TSMC's roadmap, and it wouldn't surprise me if it doesn't even exist on any formal documents outside of Nvidia, but Nvidia will give it a special name so that consumers think they are getting something unique to imply that no one else gets special sauce besides Nvidia. In reality, it's likely N5 or N5P with DTCO.

They did the same thing with Samsung's 8nm node by calling it "Samsung 8N Custom Process".

It's pulling a card out of Apple's playbook, e.g. it's not a high-resolution, high-refresh rate display; it's a Retina display with Fluid Motion.

 

[Kaluan]

From that twitter only Phoenix and N32 will be capable.
N33 has the same problem as N31 and is made on a worse process. Not sure how It can perform as RX 6700XT, unless only 1/3 of shader engines and CU od N31 actually helps.

Not sure you understood what I meant, I meant this nugget of theirs:

https://twitter.com/i/web/status/1602363036567834648

I think what they're implying is, despite N31 and N33 having similar design woes, N33 is less affected.
ie current RDNA3 bugs affect CU scaling as well

Anyway, happy to hear Phoenix RDNA3 implementation is more bug-free. Might give us insight into future dGPU revisions.

N33 vs 780M feature tests/deep dives are on my radar.

 

[moinmoin]

I think there is no cost advantage. AD103 is only 379 mm^2 of N5 related silicon and 4080 is not even using the full die. Navi 31’s GCD is 306 mm^2 of N5, along with 6 MCDs which are 37.5 mm^2 of N6. Add in its chiplet associated costs and higher VRAM amount and I think it’s clear there is no cost advantage for Navi 31.

Pure area is not the sole cost for dies. The whole reason for going for more smaller dies is higher yield. And Navi 31’s GCD is nearly 20% smaller than AD103. So the per die cost should be significantly lower for N31. The open question is the cost for packaging.

Navi3x has higher density than Ada.

Assuming Navi 3x is based on N5 and Ada based on N4 shouldn't the latter be using denser libraries, even if the density is not pursued in the eventual design? After all that's very common, e.g. essentially none of the CPUs are even near as dense as the nodes they are on would allow.

 

[jpiniero]

Pure area is not the sole cost for dies. The whole reason for going for more smaller dies is higher yield. And Navi 31’s GCD is nearly 20% smaller than AD103. So the per die cost should be significantly lower for N31. The open question is the cost for packaging

It's not like the MCDs are free, esp being on N6.

 

[moinmoin]

It's not like the MCDs are free, esp being on N6.

Of course they aren't. They should have the lowest cost factor though.

 

[jpiniero]

Of course they aren't. They should have the lowest cost factor though.

Lower, not lowest. If it was on, say SS8 or a GloFo node, maybe you could say that.

 

[eek2121]

Pure area is not the sole cost for dies. The whole reason for going for more smaller dies is higher yield. And Navi 31’s GCD is nearly 20% smaller than AD103. So the per die cost should be significantly lower for N31. The open question is the cost for packaging.


Assuming Navi 3x is based on N5 and Ada based on N4 shouldn't the latter be using denser libraries, even if the density is not pursued in the eventual design? After all that's very common, e.g. essentially none of the CPUs are even near as dense as the nodes they are on would allow.

Some people forget that intentional dark silicon is a thing.

 

[Kaluan]

Maybe some are filings for Asia/China-only or OEM-only but this is interesting:

https://twitter.com/i/web/status/1602702739641073664

Not sure why XTX is not there tho.

 

[TESKATLIPOKA]

Not sure you understood what I meant, I meant this nugget of theirs:

https://twitter.com/i/web/status/1602363036567834648

I think what they're implying is, despite N31 and N33 having similar design woes, N33 is less affected.
ie current RDNA3 bugs affect CU scaling as well

Anyway, happy to hear Phoenix RDNA3 implementation is more bug-free. Might give us insight into future dGPU revisions.

N33 vs 780M feature tests/deep dives are on my radar.

Yes, I understood you correctly.
I was just skeptical about N33 performing as N22 as the leaks suggest.
I think in mobile Ada will be better, maybe N32 will surprise us.

 

[Stuka87]

It's not like the MCDs are free, esp being on N6.

AMD has gone over this. The MCD's are "cheap" because they are on a cheap node, and there was no gain to have them on a smaller node. Having those manufactured at Samsung or GloFlo would have likely been more expensive over all. MAYBE the silicon would be cheaper. You have to remember that AMD is one of TSMC's larger customers (Number 3 after Apple and MediaTek). This means they get cheaper pricing. But if Samsung/GF were cheaper, there would still be the overhead of having to ship chips from those fabs to another location to be put on the substraight with the GCD. Plus there is always the chance those other fabs have trouble meeting demand or some other unknown. So its better to have all the parts fabbed in the same place.

 

[jpiniero]

AMD has gone over this. The MCD's are "cheap" because they are on a cheap node

N6 is not a cheap node. Cheaper than N5, definitely, but not cheap.

Edit: When AMD designed RDNA 3 several years ago, they probally thought N6 would be a cheap node by the time products launched. Which would be why they probally went with N6 rather than any alternatives.

 

[Stuka87]

N6 is not a cheap node. Cheaper than N5, definitely, but not cheap.

Edit: When AMD designed RDNA 3 several years ago, they probally thought N6 would be a cheap node by the time products launched. Which would be why they probally went with N6 rather than any alternatives.

Its the cheapest current gen node TSMC has. TSMC is transitioning N7 fabs to N6 (its the reason some re-spins of RDNA2 were on N6 and not on N7). And its important to take into account how reliable a node is. GF may be way cheaper, but if yields are bad, its not actually cheaper.

EDIT: Also, the MCD's won't need to be converted to a new node when RDNA3+ or RDNA4 come around. Which also saves costs.

 

[Geddagod]

Sorry, I just don't see "RDNA3 & Lovelace = same node" as a hill worth dying on. Particularly if whoever insists that is the case was also someone who kept harping on about how Samsung 8nm is "oh so inferior to TSMC N7P"

AMD is on a slight node backfoot, just like nVidia was last gen. The gap may be ever so slightly smaller, but it's there. And I don't exactly get what the point of pretending otherwise is.

Anyway, it's pretty clear execution and (partly) software are the culprit here. Not the node(s).

And N31 RDNA3's problems clearly go beyond just missing clock targets.


BTW AIB 7900 card reviews are out. And my 2 takeaways are
1. Bigger OC headroom than we've seen since many generations ago.
2. Building on the above, I think this stems from the vestiges of initial clocking expectations. It's clearly a 3GHz+ on air architecture, but the v/f & efficiency curve just wasn't there for them in N31's current state to market a 10-20% faster N31 AND the 50% better power efficiency.

Ur kidding me. The difference between a custom 4nm vs a custom 5nm node is way, way smaller than the samsung 10nm rebrand known as 8nm vs the tsmc 7nm used by AMD.
Also it might AIB models might clock higher, but how much extra perf are they getting from those clocks? Not much I'm guessing...

 

[Geddagod]

This. Nvidia marketing will market. You won't see a 4N node on TSMC's roadmap, and it wouldn't surprise me if it doesn't even exist on any formal documents outside of Nvidia, but Nvidia will give it a special name so that consumers think they are getting something unique to imply that no one else gets special sauce besides Nvidia. In reality, it's likely N5 or N5P with DTCO.

They did the same thing with Samsung's 8nm node by calling it "Samsung 8N Custom Process".

It's pulling a card out of Apple's playbook, e.g. it's not a high-resolution, high-refresh rate display; it's a Retina display with Fluid Motion.

Yes, but didn't Samsung 8nm exist and was called 8nm before Nvidia called their custom 8nm 8N?
Similarly, Nvidia claims they are using a custom 4nm process and called it 4N (computex hopper).

 

[biostud]

Is it really important to discuss the naming schemes of process nodes if we don't know the differences? And isn't it widely accepted that the number does not really correlate to something meaningful, hence the new Intel naming scheme? So AMD use one type of TSMC 5nm and nvidia uses another one, which they have named 4N. If anyone has any actual information on the difference, that would be great, otherwise let's look on the data we do something about.

 

[maddie]

N6 is not a cheap node. Cheaper than N5, definitely, but not cheap.

Edit: When AMD designed RDNA 3 several years ago, they probally thought N6 would be a cheap node by the time products launched. Which would be why they probally went with N6 rather than any alternatives.

What is the cost of N6? Straight answer or at least a certain range of values.

No I think, I believe, I surmise. These definitive statements demand some level of proof or they are useless attempts to insert superior knowledge into an argument.

 

[eek2121]

What is the cost of N6? Straight answer or at least a certain range of values.

No I think, I believe, I surmise. These definitive statements demand some level of proof or they are useless attempts to insert superior knowledge into an argument.

Several thousand dollars cheaper. N6 is cheaper because using EUV meant less machine time which meant TSMC could sell more wafers. A bit after it hit HVM, the price I heard was $4,000-$5,000 vs. $7,000-$8,000 for N7. That was from a reputable source. Prices have gone up for everything since then, but it is still much cheaper than N7 and N5.