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Speculation: Keller's role at Intel

What will Jim Keller's legacy at Intel be?


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Vattila

Senior member
Oct 22, 2004
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As many of you will know, Jim Keller, the CPU architecture design guru, joined Intel in April this year, to lead the company's silicon engineering, in particular SoC development and integration (news release). What do you think his primary role and influence will be at Intel?

Recently, as part of my speculation about the current and future prospects of Intel's integrated design and manufacturing model, I was struck by commentary that pointed out how interwoven chip design and manufacturing process are at Intel, and how different this is to the foundry model, where automation, standard cells and design libraries abstract much of the manufacturing details, and hence creates a simpler, more efficient and more flexible design flow for the chip designer, albeit with the loss of some control and optimisation.

This made me think back 10 years to the days when ex-CEO Dirk Meyer at AMD dealt with a similar issue, grappling with going fabless, and the integration of AMD and ATI, and their different design cultures — ATI being used to the foundry model, while AMD was still ingrained with the integrated model. I seem to recall that there was discontent from some of the old-school chip designers, who disliked the disruption, and were reluctant to move to a foundry model with new design tools and methodologies.

With this in mind, it occurred to me that maybe Jim Keller's primary role will be to oversee a similar transition at Intel, adopting a nimbler chip design business model, more akin to the fabless and foundry models, and thus more in line with the industry common practice. These changes would make Intel's design and manufacture divisions more independent and flexible, allowing the design division to more easily purchase wafers externally if necessary, and allowing the manufacturing division to operate more like a common foundry, hence attracting external customers.
 
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maddie

Platinum Member
Jul 18, 2010
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Laughing at these threads. Don't mind them at all as new products are thin these days, and we need to keep the arguments going.

With regards to details of Keller's work at Intel. Haven't a clue
 
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Markfw

CPU Moderator, VC&G Moderator, Elite Member
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May 16, 2002
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I must say, since the 2700x, there has been little to no news or products, But after a while speculation does get boring as well.

As to Kellers role, its way too early for me to even speculate.
 
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DeathReborn

Platinum Member
Oct 11, 2005
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Just out of interest, are these speculation threads some sort of project for School/Work purposes?
 

NostaSeronx

Platinum Member
Sep 18, 2011
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He is probably going to be working on VISC SoC, eventually. Under the VISC mentality at Intel, it should do everything.

Sponsored by Intel Parallel:
(1) diverse parallelism models; (2) diverse memory architectures; and (3) diverse hardware instruction set semantics. We believe that these issues must be addressed using a language-neutral, virtual instruction set layer that abstracts away most of the low-level details of hardware, an approach we call Virtual Instruction Set Computing.

The key novelty in our work is that our instruction set exposes a very small number of models of parallelism and a few memory abstractions essential for high performance algorithm development and tuning. Together, we expect that these abstractions will effectively capture a wide range of heterogeneous hardware, which would greatly simplify major programming challenges such as algorithm design, source level portability, and performance tuning.
--- Intel recent employees: [Random Quotes to get the gist]
Staff Engineer @ Intel to 2009:
Enhanced multi-core microprocessor, near-cycle-accurate, micro-architecture simulator (DANTE) for Itanium-2 Processors by enabling virtual to physical addressing, result increased modeling fidelity.
HPE/Itanium

Principal Engineer @ Soft Machines to 2016:
Definition of CPU architecture; Instruction set encoding and specification; Architectural Simulation; driving performance engineering.

Principal Engineer @ Intel to Current:
CPU Architect

New micro-architecture is definitely a given. Generally, the VISC from Intel is going to scale across at least CPU and GPU. Hence, why it probably important to have Jim Keller(SoC) and Raja Koduri(GPU) together.
 
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Vattila

Senior member
Oct 22, 2004
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An AnandTech Exclusive: The Jim Keller Interview

"In the last two decades, Jim has overseen a number of pivotal products, but it bears mentioning that modern processor engineering teams are massive groups working on 3-7 year development cycles, perhaps more. In previous companies, Jim has been tasked with developing teams as well as performance, but now that he is under the umbrella of Intel's big development behemoth – officially focusing on 'SoC Development and Integration' – one of the key areas will be how a company the size of Intel, which already has a number of good engineers, can get the best out of a rockstar like Jim Keller."

anandtech.com

The interview gives me the impression that he is indeed at Intel primarily to strengthen their executive team — i.e. to oversee and direct the enormous engineering organisation, ensure it operates optimally and lay out a reliable and competitive roadmap. It doesn't sound like he was hired specifically to work on a next-gen CPU architecture. His position sounds more administrative than that would suggest.

However, after reading the interview, I am now more doubtful about whether he will implement radical changes to the way Intel designs and manufactures chips (to better align Intel with fabless design houses and pure-play foundries, as I conjecture). I do suspect that he will be a broad problem solver and strategic planner, but perhaps that will be the extent of his work and legacy at Intel.
 
Mar 11, 2004
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An AnandTech Exclusive: The Jim Keller Interview

"In the last two decades, Jim has overseen a number of pivotal products, but it bears mentioning that modern processor engineering teams are massive groups working on 3-7 year development cycles, perhaps more. In previous companies, Jim has been tasked with developing teams as well as performance, but now that he is under the umbrella of Intel's big development behemoth – officially focusing on 'SoC Development and Integration' – one of the key areas will be how a company the size of Intel, which already has a number of good engineers, can get the best out of a rockstar like Jim Keller."

anandtech.com

The interview gives me the impression that he is indeed at Intel primarily to strengthen their executive team — i.e. to oversee and direct the enormous engineering organisation, ensure it operates optimally and lay out a reliable and competitive roadmap. It doesn't sound like he was hired specifically to work on a next-gen CPU architecture. His position sounds more administrative than that would suggest.

However, after reading the interview, I am now more doubtful about whether he will implement radical changes to the way Intel designs and manufactures chips (to better align Intel with fabless design houses and pure-play foundries, as I conjecture). I do suspect that he will be a broad problem solver and strategic planner, but perhaps that will be the extent of his work and legacy at Intel.
I agree. I think he's there to give them focus. I think Intel's biggest problem has been figuring out what is the next big thing these days. They missed big on mobile (by that I mean small SoCs). I think the problem is less that they don't see what the next big thing is, and more that they can't seem to figure out how to go about making a product for it. They have enough resources (engineering, money, and marketing) to still do well, but even their successes almost seem in spite of themselves. Like Athlon 64 showing them the potential of Pentium M. And then AMD buying ATi in order to start moving towards mixed CPU/GPU chips. Or Apple showing them how to make modern svelte powerful laptops (that Intel used to push their Ultrabook platform to get the Windows side doing that; but then that also took Microsoft scaring the OEMs with the Surface products to get them to really push the potential of those devices). Actually I'd say its not necessarily even that Intel needs others to show them (as I expect they have plenty of internal teams with great ideas), but rather that they need someone to properly take the reigns of that vision and set them on a course to actually develop it. I think that's what made Atom a fiasco instead of a success, they just didn't have any real long term plan/vision to execute on. And they often rarely seem to have that, just focused on iterating bit by bit until they're forced to change.

I think Intel is hoping Keller will bring more of the Athlon 64/Zen/Sandy Bridge/Core 2 type of moments, where its executing a good idea well. I think they're looking at him setting the vision for their CPU and GPU, and that they think him and Raja will be a good fit to do that. Will be interesting to see how they go. I think there's 3 stages they'd be looking. The first is bolstering the iGPU and making it more than mostly media processing and light gaming, so that they can do more single chip solutions for laptops, SFF PCs, and other slim profile designs. Then it is pairing CPU and GPU as separate chips in the EMIB. And the third is datacenter stuff, figuring out how to cram as much power and determining the proper ratio of CPU/GPU power - along with memory, storage, etc - to meet the market changes. I'm curious if it might also be for looking at integrating the GPU and CPU logic (I recall AMD talking about that, and them saying that is the next step for Bulldozer type design and was the impetus behind the Bulldozer design, as I believe they planned on bolstering the floating point power that it was lacking by integrating GPU logic which is more tailored to that), so as to maximize the CPU/GPU processing ratio at the transistor level (so if you could find some fairly optimal ratio, then things just become scaling it up to the market).

I think the other important piece that Intel needs to iterate on, is integrating communication block into their chip packaging (I expect EMIB), but integrate LTE/5G, wifi, bluetooth, and any other wireless (display would be a big one). Oh and 10G wired too. And Thunderbolt.

That would be an interesting new development for Keller that Intel uniquely offers. And the storage stuff is another (they definitely seem to need someone to give them a vision/plan for 3D Xpoint).
 
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bbhaag

Diamond Member
Jul 2, 2011
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I thought it was a great interview. It was nice to see Anandtech pick up a big name like Keller for a one on one even if the the questions were softballs. Anyway, it seems like Keller was brought in to manage teams at Intel not necessarily lead a small team on a ground breaking tech but who knows he could just be leading us on. Pretty cool read though. Thanks for linking it Vattila.
 
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Vattila

Senior member
Oct 22, 2004
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Another interview at VentureBeat:

Why rock star chip architect Jim Keller finally decided to work for Intel

"I don’t know that I look at it and think, “I need a from-scratch x86 core.” There’s a lot of methodology changes that are rolling through the industry as CAD development moves forward. I see it as there’s some methodology stuff that’s interesting to work on, and then there’s the application of some of the processors to new problems that’s interesting. And then whether we do a new core or rewrite something is more of a tactic than a strategy."

https://venturebeat.com/2018/07/16/why-rock-star-chip-architect-jim-keller-finally-decided-to-work-for-intel/2/

Interestingly, the quote above is in response to a direct question about designing a fresh x86 core. His answer seems to refute that and hint somewhat in the direction of my conjecture, i.e. that he will implement methodology changes.
 
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ultimatebob

Lifer
Jul 1, 2001
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Maybe Intel will finally fall into line with AMD and start buying into the "MOAR COREZ!" methodology of improving desktop CPU performance.

Oh wait... that's already happening ;)

But, seriously, I hope that his team(s) will finally develop a mobile SoC that's worth a damn. Time to give Apple and Qualcomm a run for the money.
 

Vattila

Senior member
Oct 22, 2004
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Interesting talk by Jim Keller, Intel SVP and GM of the Silicon Engineering Group:


In summary, he seems genuinely upbeat about the future for chip design and performance scaling, and he reveals some very interesting tidbits about what he's working on at Intel.

My notes:

- shakes head when introduced as the man behind Zen (thinks credit belongs to Zen lead architect, AMD Corporate Fellow, Mike Clark, perhaps?).

- muses on the failed predictions of the end to progress (Moore's law in particular).

- gives lots of examples of the exponential evolution in the silicon industry.

- presents fascinating examples of how masks for DUV lithography are printed (in psychedelic patterns) to cleverly interact with the wide 193nm light to produce simple and precise patterns of smaller features, demonstrating the immense progress enabled by ingenuity despite the limitations of DUV.

- firm believer in transistor scaling for the foreseeable future.

- posits that the curve of progress is driven by specific technologies, which predictably will follow a local S-curve of diminishing returns, but will inevitably be replaced in turn by innovative technologies, which again will follow a local S-curve, and on and on (e.g. planar CMOS transistors to FinFET, DUV to EUV lithography, 1D to 2.1D to 3D packaging, etc.)

- sees clear path to 3X fin-pitch scaling from 10nm.

- tasked engineers at Intel with envisaging 100x transistor scaling, and after only three weeks they presented 50x (well, 48x) path for transistor scaling from 10nm FinFET: 3x with fin-pitch scaling, 2x with nano-wire, 2x with stacked nano-wire (vertical CMOS; NMOS over PMOS transistor, rather than side-by-side, giving smaller standard cell size), 2x with wafer-to-wafer stacking, and another 2x with die-to-wafer stacking.

- thinks single-thread scaling has been limited by "mindset", and "we're actually going to do something about it" (interesting!).

- has a strong belief in manufacturer's ability to bring down cost and simplify process (almost slips and reveals how many days a 14nm wafer at Samsung takes through the fab, but stops himself and just says "you would be amazed how simple it is").

- talks about abstraction layers, branch/data predictability and microarchitecture evolution.

- mentions DEC Alpha EV6, their first big out-of-order machine, which he architected, with a 20 instruction window, 100 instructions in flight, then compares that with Sunny Cove with 800 instruction window, which sustains between 3 and 6 x86 instructions per clock.

- working on a CPU generation that is "significantly bigger" than Sunny Cove and closer to the "linear curve on performance", noting that "this is a really big mindset change" (on single-thread scaling, I presume).

- sees so many "different places that we're doing innovation", relating to processor performance, that he really doubts "we're hitting some kind of limit", despite what "lot's of people think".

- refers to "Raja's law"; a new architecture every 10 years (single-core, multi-core, GPU, discrete AI), each architecture with diminishing returns over 10 years.

- optimistic about future progress and innovations — muses on theoretical physicist Richard Feynman's statement that there is "plenty of room at the bottom".

- praises open-source.

- Q&A on AI: thinks architecture is open-ended for now; CPU, GPU, fixed-function accelerator; silicon production allocated to each may evolve from 80/20/0 percent to 33/33/33 over time.

- Q&A on semiconductor businesses declining in number: GF given up on 7nm, but they have a "huge business doing other technologies", optimistic about fab investment and future, no shortage of money and appetite for fab space.

- Q&A on voltage and frequency scaling: they are working on it; cannot disclose frequency numbers, but they are pretty good (noteworthy, not as downbeat on frequency as AMD has been lately).

- Q&A on FPGA: "we build FPGA models of everything we do now", "they're the heart of all the emulation technology we have".

- Q&A on cost (non-recurring engineering): diverse and wide range depending on product and node, from $2 million to $2 billion, $5 to $10 million for masks alone at 7nm.

- Q&A on materials: "we have only scratched the surface".

- Q&A on Quantum Computing: "not so sure about that", "we haven't really gotten the results that we expect, but they are making progress".

- at the end, some general musing about his own background, and some advice to students: find a workplace with enthusiastic people, or be a "change agent"; "I worked at AMD after they fired half the people — it was not a happy place, but my conviction was that if we go do the right thing, design the right thing, put our energy into it, we'll do something cool — now it's a happy place".
 
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NTMBK

Diamond Member
Nov 14, 2011
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Intel was overconfident about 10nm, I'm in no way surprised that they continue to be overconfident.
 

Ajay

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Jan 8, 2001
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Intel was overconfident about 10nm, I'm in no way surprised that they continue to be overconfident.
Fair point; if Intel cannot get 7nm EUV out with good yields, nothing Keller does will matter.
 

Nothingness

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Jul 3, 2013
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Intel was overconfident about 10nm, I'm in no way surprised that they continue to be overconfident.
Yeah that's funny to hear them talk about Moore's "law".

OTOH the hint at a new micro-architecture gets me curious. And I have more confidence in Intel in that department.
 

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