oobydoobydoo
Senior member
- Nov 14, 2014
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Haha.
I hope they are right, I really do. All this secrecy though... it worries me.
Haha.
I hope they are right, I really do. All this secrecy though... it worries me.
The reason you are seeing a relatively small advancement in ST perf/clock is because Intel has spent the last few generations re-targeting the power profile of its chips. Also, in a design like Haswell, you can get a significant boost in performance if you utilize the new instructions such as AVX2.
I think with Core at a sufficiently low power level, future improvements can target raw performance increases.
If Intel could have improved IPC more with their current uArch as base they would have. That would have benefited their low power CPUs too.
They need to improve that IPC while at the same time keeping "C" constant and power consumption flat-to-down.
Example is the SHA score with no improvements when Skylake should have a new extension for it.
That WCCF rumor sounds so bombastic...
Here have my rumor:
http://browser.primatelabs.com/geekbench3/1753502
This looks like it's a Skylake early sample (GenuineIntel Family 6 Model 94 Stepping 1) and it' the same as this one probably (22 January 2015):
I thought CannonLake gets some SHA extensions: http://forums.anandtech.com/showpost.php?p=36982604&postcount=1202
Geekbench score looks very good if this is a SKL for this low clock especially MT score. Only 15% slower than a much higher clocked i7-4770K.
What exactly is crap? Do you have more infos about "MorphCore"? I don't understand your AVX-512 comparison (not to mention that Client Skylake most likely won't support AVX-512)
I don't see any reason why the desktop version of Skylake shouldn't support AVX-512 since it has many performance benefits for a lot of consumer applications seeing as how Intel went there way to push TSX on some Haswell processors and soon for almost every Broadwell Processor plus that only benefits lock-free data structures ...
AVX-512 + TSX is an extremely effective combination for aggressively exploiting parallelism ...
If I wanted TLP I would get a GPU or a xeon phi, MorphCore would be the last thing I would think about ...
It's gotta be that MorphCore![]()
I don't see any reason why the desktop version of Skylake shouldn't support AVX-512 since it has many performance benefits for a lot of consumer applications seeing as how Intel went there way to push TSX on some Haswell processors and soon for almost every Broadwell Processor plus that only benefits lo
Just a guess, but notice that CNL is expected to feature AVX-512. This implies to me that there is either a power, area, or time-to-market reason that AVX-512 was disabled on the consumer Skylake since consumer Cannonlake will have it. I don't think it's for artificial segmentation purposes.
My bet would be on it being to speed up time to market so that they don't end up with another TSX-like fiasco.
Like AVX2 there is almost no productive application available for consumers. It mainly helped stress tester like Prime95, for Intel this was a disadvantage for Haswell in many temperature and power tests. And by the way it is Intel who confirmed that AVX-512 is Xeon only.
It's gotta be that MorphCore![]()
I bet its HBM.
Wouldn't it be possible to move all the system memory into RAM and just have no storage at all? Like what the PS4 and Xbone have.
Extending support for a wider SIMD instructions isn't exactly hard since Intel has done it twice already ...
I highly doubt that AVX-512 wouldn't be included in the consumer versions since the server versions are using the exact same core micro architecture as the consumer ones so pushing it fast to the market without the consumer versions doesn't make much sense when their implementations are identical ...
Would you pay more money for a laptop chip with AVX-512? Probably not. Would you pay more money for a server chip with AVX-512? Probably.
That's really all that needs to be said about why it looks like AVX isn't on the consumer parts. Intel has gotten pretty good about doing multiple die splits to keep die size down to drive down cost. Why not the cores too?