Discussion Should ARM design a Cortex A615 core ?

[FlameTail]

As the title implies, I think ARM should design a Cortex A6xx core that sitsvin between the A7xx and A5xx.

Why do I think it is necessary? Because Apple of Apple's Efficiency cores.

Apple's efficiency cores (icestorm, thunder, blizzard etc..) are far more powerful than ARM's own efficiency cores (A5xx). They reach almost Cortex A7xx levels of performance while consuming similar power to an A5xx core, which is crazy.

Apple achieves this by making their efficiency cores much larger, and with Out-of-Order Execution.

Whereas, the Cortex A5xx series cores are measly small in comparison and have in-order execution.

So the hypothetical A6xx cores would be like an enlarged A5xx but with OoO.

I think the A6xx cores would be useful in laptop chips (A5xx cores are ridiculously weak for a laptop), and some Mobile chips may use it too. I can imagine that Google would love to put a Cortex-X + Cortex-A6xx in their custom Tensor chips, in a similar vein to the 2+4 configuration in Apple's Bionic chipsets

 

[DrMrLordX]

Yes, they should. ARM has been very slow to improve their smaller cores.

 

[Lodix]

The name doesn't matter, the problem is that ARM doesn't look to be able to design a competitive low power CPU as Apple.

And if they did it would in the 5 family because of its nature of efficient core and as you said they don't use more power than a Cortex A5xxx.

 

[gdansk]

Maybe. Or rather scale the X series up to near FireStorm levels of performance. Keep A7xx series in-between. With A5xx in-order but more efficient at the end.

Much easier said the done but it seems that's their long term objective: 3 competitive core types for smartphone chips. But so far they've been far behind Apple's two core types.

 

[NostaSeronx]

Isn't there already a core in between 5-series and 7-series? Being the 6-series with the Cortex-A65.

It probably should get a successor, since it is getting usage:

https://sima.ai/wp-content/uploads/2022/07/SiMa_ProductBrief_R12.pdf

Is compared against A55 in the MIPS i8500 showcase:

【大原雄介の半導体業界こぼれ話】 ライセンスビジネスに見る「Arm」と「RISC-V」の関係

5月10日、MIPSは最初のRISC-Vプロセッサというか、RISC-V命令をサポートする最初のMIPSプロセッサとして「eVcore P8700/I8500」を発表した。現状ではまだP8700/I8500の本当の意味での詳細は明らかではないのだが、

pc.watch.impress.co.jp

https://asset.watch.impress.co.jp/img/pcw/docs/1410/878/photo05_o.jpg

Samsung India has already ported it to 4nm:
[Owned PNR of Cortex A65 Quad Core CPU at frequency 2.2GHz, 4nm Tech Node]

 

[DrMrLordX]

With A5xx in-order but more efficient at the end.

The issue seems to be that Apple is iterating upon their small cores to improve IPC and/or clockspeeds without significantly increasing power usage. ARM isn't really doing that (yet).

 

[soresu]

I think the A6xx cores would be useful in laptop chips

IMHO Cortex Axx/xxx little cores are inadequate for laptop use beyond very basic stuff.

That's why Snapdragon 8cx Gen3 uses X1 and A78 cores, and it's successors will likely do the same thing.

 

[FlameTail]

Here's what I envision the lineup should look like-

Cortex X series -> 8-wide
Cortex A7xx -> 6-wide
Cortex A6xx -> 4-wide
Cortex A5xxx -> 2-wide

Ngl, that looks very nice on paper, but I guess that makes sense in practice too.

 

[Thala]

I think the A6xx cores would be useful in laptop chips (A5xx cores are ridiculously weak for a laptop), and some Mobile chips may use it too. I can imagine that Google would love to put a Cortex-X + Cortex-A6xx in their custom Tensor chips, in a similar vein to the 2+4 configuration in Apple's Bionic chipsets

The small cores are already gone for laptop chips like the 8CX Gen 3 - where only large and medium cores are used - similar to Apple. Going below the 7 series like the Cortex A78 for medium cores is pointless for laptops.

 

[FlameTail]

https://www.reddit.com/r/hardware/comments/yjkxp7

Even SiFive made an Out-of-Order efficiency core.

Since SiFive and Apple have already made competent efficiency cores, I think it makes sense for ARM to make an OoO efficiency core as well

 

[DrMrLordX]

Even SiFive made an Out-of-Order efficiency core.

To be fair, the performance of those cores produced by SiFive probably isn't in the same ballpark as even A510.

 

[NostaSeronx]

To be fair, the performance of those cores produced by SiFive probably isn't in the same ballpark as even A510.

Instructions per seems to favor cortex, but area and frequency favors P470.
>1.88 GHz A55/>2 GHz A510 is less perf than the ~3 GHz(7nm)/~3.4 GHz(5nm) P470 demos.

In this case, P470 can probably replace 2xA76/6xA55 machines with 8x P470 with less area/power. While pushing <16-core P470 solutions, if they want to do the game console/handheld dream.

Also, have Qualcomm thirsting for RISC-V(P470/P670 announcement) from SiFive:
“We are excited to see RISC-V solutions for wearable and consumer devices becoming a reality, and we are looking at possibilities of integrating SiFive’s latest products into Snapdragon platforms,” said Ziad Asghar, Vice President, Product Management- Snapdragon Technologies and Roadmap at Qualcomm.

No Cortex-A6xx means that Qualcomm has been doing Cortex-X3/Cortex-A715/Cortex-A710/Cortex-A510. Where I would assume 1x A710 would become a A715 and 1x A710/3x A510 would become a A6xx. The in-order part of A510 is chugging the phone/compute platforms down.

P670/P470 with Samsung's three libs: High Performance(SF3E), High-Efficiency Performance(SF3E), High Density(SF3E). Will probably beat the lower-end current ARM mobile/compute platforms by Qualcomm.

 

[Thala]

P670/P470 with Samsung's three libs: High Performance(SF3E), High-Efficiency Performance(SF3E), High Density(SF3E). Will probably beat the lower-end current ARM mobile/compute platforms by Qualcomm.

You probably missed the memo, that Qualcomms compute platforms only contain X- and 7-series cores since 2021. It probably beat the Qualcomm compute platforms from 2018 - but who cares. And this is before we are talking about ARM64 and x64 emulation, which would be required for both Android and Windows.

 

[NostaSeronx]

You probably missed the memo, that Qualcomms compute platforms only contain X- and 7-series cores since 2021. It probably beat the Qualcomm compute platforms from 2018 - but who cares. And this is before we are talking about ARM64 and x64 emulation, which would be required for both Android and Windows.

Snapdragon 7c/7c Gen2/7c+ Gen3 => 2x A76+6x A55 & 4x A78+4x A55 :: where P670/P470 would replace prior ARM cores, while QC's internal custom RISC-V would replace X-series for 8-series+.
Small OoO would largely dominate the entry-market of compute, and premium-market of mobile.

ARM64 doesn't need to be emulated, transpilers are available for ARM<->RISCV, UWP patches would include RISC-V capability eventually.
ptitSeb's work will probably lead to x86-64(Box64 RV64GC) and x86-64-32(Box32 (still internal)) emulation or force Microsoft to get it off its 2023 backlog.

Android isn't a huge issue as Microsoft/Qualcomm is concerned: https://lists.riscv.org/g/sig-android/message/74
We would however see a developer kit before actual support: https://www.qualcomm.com/news/relea...ows-pcs-now-available-cost-effective-resource

 

[Thala]

Snapdragon 7c/7c Gen2/7c+ Gen3 => 2x A76+6x A55 & 4x A78+4x A55 :: where P670/P470 would replace prior ARM cores, while QC's internal custom RISC-V would replace X-series for 8-series+.
Small OoO would largely dominate the entry-market of compute, and premium-market of mobile.

You are dreaming of some non-existing cores. The topic is about P670, which does not even match the integer performance of Cortex A-78. Perhaps some very low-end devices, which suffer even more under dynarec.

ARM64 doesn't need to be emulated, transpilers are available for ARM<->RISCV, UWP patches would include RISC-V capability eventually.
ptitSeb's work will probably lead to x86-64(Box64 RV64GC) and x86-64-32(Box32 (still internal)) emulation or force Microsoft to get it off its 2023 backlog.

Box64 is only available as dynarec for x64/x86->ARM64. Everything else is interpreter. And even the dynarec is not particularly fast. I am getting 465 in Geekbench SC under the dynarec, while my native SC score is 1250. Thats only 37% of native speed - so already very slow.
For RISC-V we are talking about interpreter, which is 10 times slower.

Android isn't a huge issue as Microsoft/Qualcomm is concerned: https://lists.riscv.org/g/sig-android/message/74

It is barely booting up. It does not give confidence in a production ready solution - even without the transpiler issues mentioned above.

 

[NostaSeronx]

You are dreaming of some non-existing cores. The topic is about P670, which does not even match the integer performance of Cortex A-78. Perhaps some very low-end devices, which suffer even more under dynarec.

The direct competitor to an A615 which is the actual topic, would be the P470. The closest ARM relative is a re-iterated A72 like Phytium's FT663. As is that has good-enough emulated performance on Linux on ARM.

Box64 is only available as dynarec for x64/x86->ARM64. Everything else is interpreter. And even the dynarec is not particularly fast. I am getting 465 in Geekbench SC under the dynarec, while my native SC score is 1250. Thats only 37% of native speed - so already very slow.
For RISC-V we are talking about interpreter, which is 10 times slower.

ptitSeb stated once hardware arrives the software will get dynarec for x86/x64/x32(x86-64 32-bit) to RISC-V. However, Microsoft's version will most likely be based off its ARM version.
Native ARM UWP = Native RISC-V UWP, once they pop it out. Given Qualcomm it will require P670/P470 for NEON/SVE/RVV shared paths. Thus, the x86/x86-64 on ARM64 will also give RISC-V/RVV paths if RISC-V is detected. The RISC-V support is backlogged for 2023, so I don't know when it will get forwarded to work on it now phase. For Microsoft to even develop, they would still need hardware of which Qualcomm is going to be the major source.

It is barely booting up. It does not give confidence in a production ready solution - even without the transpiler issues mentioned above.

People are already developing for RISC-V without major modern hardware. So, it is likely to have high confidence when money is placed in the equation.

----
As is right now a hypothetical Snapdragon 5c/6c, leaning heavily on that that c can be:
8x High-Efficiency Perf P470s
8x High-Density P470s
Extended Examples of SiFive's 16-core cluster manager:
7c variant => 8x P670/8x P470
8c variant => 8x 2019-RISC-V(FalkororSaphira-derived(Pre-Nuvia RISC-V core)) developed core/8x P670.

(There are custom cores at Qualcomm as hinted in the image... of which started immediately after Falkor/Sahpira ARMv8.2 and ARMv8.4+SVE were dropped)

With the existing Cortex cores and cluster manager:
4x A510s at Hi-Eff Perf
8x A510s at High Density.

The P470(latest SiFive OoO small core) 5c/6c would curb stomp the latest InO small cores of an ARM 5c/6c. ARM as is definitely needs a small OoO core, hopefully dropping SMT2 from A65 for a L0 cache in A6xx.

 

[dark zero]

They should? They MUST.
To be fair, the In-Order Execution Cores are no longer useful for phones.

is better to pull only Out of Order cores now. The improvements might be noticeable with that

 

[FlameTail]

To be very clear, the A615 core I am proposing is a direct alternative to Apple's efficiency cores, which have OoOE. Apple's efficiency cores are far more powerful than ARM's "A510" efficiency core, but the Apple E-core is also below the Cortex A715 in performance, but multitudes more efficient.