September 22nd ETA for AMD FX processors

[MisterMac]

half strength implies what it implies.

If i can lift 50kg half the strength is 25kg. So you need to do double the lift with 25 to get the 50kg movement.

So lifting a 50kg bag 3000times a day the other guy would need to lift his bag 6000 times a day..



also Bd has alot more l1 cache and l2 cache than SB so by that strength measurement (ridiculous analogy ..) BD would be a few times stronger than SB.

Again lopsided analogies.


What if BD(25KG) can lift two bags in one trip? 2x25?
And SB(50) only 50 KG in one trip?

Then what?


Your putting performance basicly @ one area and then strawmanning that bd needs double FPU's or DOUBLE clockspeed to win over sandy.

Grow up.

No matter how you pull out, most rumor drama engineering early steppings blabla, points towards BD needing those 2 trips @ 25kg to match sandy.

Which from a future perspective makes BD look grim - as more cores, more heat, more tdp.

But yea, please keep posting like a rebellish teen.

 

[NostaSeronx]

also Bd has alot more l1 cache and l2 cache than SB so by that strength measurement (ridiculous analogy ..) BD would be a few times stronger than SB.

L2 cache* and L3 cache*

Both of which are 8MB

L1i is bigger but shared between the cores

L1d is smaller

 

[BlueBlazer]

What happens if it does with 8 cores? - any opposing side will tell their customers:
"Yes well our tech is so good, we need HALF of their cores to beat them".

Your setting yourself up for failure.

That happened before >> [Microprocessor Forum] 8 Intel cores faster than 16 AMD cores! (video). And lots of press and forums had a field day with this one.

If i'm correct a dual Quad core Xeon Core Duo @ 2Ghz will get his ass whiped by SB 2600 in 8threaded applications..

So those 8core Xeon from back then are no more cores!!!! they were 8cores back then, but now they are effectively promoted to a quad core!!!

Huh? Cores are cores, and Core i7 2600K has 4-cores (make no mistake about that). I was referring to Bulldozer versus Sandy Bridge (as well as Sandy Bridge-E). And AMD by labelling Bulldozer as "8-core" CPU are stimulating high expectations on fans to see it beat the competition's (Intel) 4-core and 6-core CPUs. Just imagine when those expectations aren't looking good..... :hmm:

Why don't you answer my questions when i ask you what performance a core should deliver to be called a core?
you are arguing that a core is defined by its performance... so ? Maybe over 5years we can say... a quad core SB isn't a quad core... its 1core look at the performance compared to todays core's!

Question from earlier? Not sure I saw that. As for that, the core must be able to deliver almost 100% of its total performance at all the time when fully utilized, to be qualified as a core. Thus when all cores are fully utilized, each core must be able to deliver the same performance. However if the "core" does not behave in such a manner when all "cores" are fully utilized, then it is likely that the "core" is a virtual/logical core or hardware thread (either SMT or CMT).

Just to give you guys an idea of who we're dealing with, here are some of NostaSeronx's posts from over at OCN (his username there is just Seronx). I'm assuming he added the "Nostra" in because of his definite claim that Bulldozer would be released in August.

Yups, at OCN he was often proven wrong with his fallacies. Gives some meaning to the word radicalism...

You're right, that totally ruined the message of my post.
How will anyone even get the point - i was trying to make.

Useless post is useless.

I'd put him (SeronX) on ignore. He just want some attention...

 

[996GT2]

Yups, at OCN he was often proven wrong with his fallacies. Gives some meaning to the word radicalism...

I'd put him (SeronX) on ignore. He just want some attention...

QFT

 

[Riek]

Question from earlier? Not sure I saw that. As for that, the core must be able to deliver almost 100% of its total performance at all the time when fully utilized, to be qualified as a core. Thus when all cores are fully utilized, each core must be able to deliver the same performance. However if the "core" does not behave in such a manner when all "cores" are fully utilized, then it is likely that the "core" is a virtual/logical core or hardware thread (either SMT or CMT).

ok that is at least a more valid approach than what I understood from your previous remarks.

But to respond to that, a core will always have performance loss when all the cores are loaded.

Even if you assume the perfect program, you still have a shared memory controller, shared l3 cache, shared l2 cache in some cpu's. So that is nothing new.

I don't think anybody disagrees that a shared design has drawbacks but it also has merits.

Ofcourse talking about cores is symantics, but we had shared logic for very long time now.

-first we had single cores in multiple sockets sharing the same northbridge
-then we had single cores in multiple sockets both having their own northbridge but shared through the ram through the cores
- then the dual cores came with shared northebridge
- then the dual cores came with shared northbridge and shared l2 cache.
- then the quad cores came with shared northbridge and shared l3 cache.
- now the dual cores come with shared front end, fpu, l2 cache, l3 cache and northbridge


You can say it is HT like that it gives a bigger performance penality then a conventional dual core design. But if you shut down the core in a HT cpu the second thread won't work either, if you shut down a core in BD the other core will still work.

One thing to note about BD is that:

The threads are handled completely undependant from eachother.
The front end is shared, but it works only for 1thread/cycle.
The fpu is shared, but the fpu sheduler only accepts 1thread/cycle.



Can you think about the following concept?

You look it at this moment from this angle (correct?):
you take one core performance, you add the other core and the overal performance drops more than you would expect from a second core. so the core's are not real cores.

But try to look it from another angle (the multithreaded angle)
You have 2 cores that give a certain performance and when you only use one core it becomes faster than what you would expect.

both scenario's are exactly the same, but they give a completely different notion to the result imo.

Also i believe you overestimate the drawbacks of the shared design. while you can indeed stall shared resources, for real software this is not the case. In most cases the software used in real life will never use all the execution resources. Most of the times, the most intensive software is the least execution intensive software.

 

[LOL_Wut_Axel]

how is Movieman an intel person?

He used to be an intel person, but he's over at the AMD camp as far as i can recall as of reciently.

And Chew always been an AMD person.
He even brings down AMD rigs to setup and display and OC @ the XS parties.
Really cool guy... :biggrin:

And yes i heard about the invite to AMD @ TX b4 u guys even heard about it.
Dave even told me he saw an article writer from AT there, so u can expect AT will have an article on it too.
But once again.... they only broke 1 record... a ghz record.

That is all, why? Because from what i heard from the guys there, and from more then 1 source... all that GHZ translated to erm... disappointment on a real speed scale.

How is this NOT obvious to people still? Come on, they're pricing an Eight-Core, 3.1-4GHz CPU against a Quad-Core, 3.3-3.8GHz CPU. That should tell you everything, and that is that it has eight weak cores and to try and counter a bit for that deficit they ramp up the clock speeds. It also has a deeper pipeline than Sandy Bridge, to facilitate those higher clock speeds in the first place even if it means losing some IPC.

The only chance it has is in multi-threaded applications, as that's always where many parallel slow cores do better than lesser, faster ones. Even then, if IPC is low enough and they lose too much performance from the module concept, it wouldn't look very good. It makes more sense every time I look at it: Bulldozer was meant to be a server CPU first and foremost. Sandy Bridge makes more sense for desktop workloads.

 

[NostaSeronx]

The threads are handled completely undependant from eachother.
The front end is shared, but it works only for 1thread/cycle.
The fpu is shared, but the fpu sheduler only accepts 1thread/cycle.

The AMD Family 15h processor floating point unit (FPU) was designed to provide four times the raw
FADD and FMUL bandwidth as the original AMD Opteron and Athlon 64 processors. It achieves this
by means of two 128-bit fused multiply-accumulate (FMAC) units which are supported by a 128-bit
high-bandwidth load-store system. The FPU is a coprocessor model that is shared between the two
cores of one AMD Family 15h compute unit. As such it contains its own scheduler, register files and
renamers and does not share them with the integer units. This decoupling provides optimal
performance of both the integer units and the FPU. In addition to the two FMACs, the FPU also
contains two 128-bit integer units which perform arithmetic and logical operations on AVX, MMX
and SSE packed integer data.
A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC
performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX
and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute
instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which
supports up to two 128-bit loads and one 128-bit store per cycle.
FPU Features Summary and Specifications:
• The FPU can receive up to four ops per cycle. These ops can only be from one thread, but the
thread may change every cycle. Likewise the FPU is four wide, capable of issue, execution and
completion of four ops each cycle. Once received by the FPU, ops from multiple threads can be
executed.
• Within the FPU, up to two loads per cycle can be accepted, possibly from different threads.
• There are four logical pipes: two FMAC and two packed integer. For example, two 128-bit
FMAC and two 128-bit integer ALU ops can be issued and executed per cycle.
• Two 128-bit FMAC units. Each FMAC supports four single precision or two double-precision
ops.
• FADDs and FMULs are implemented within the FMAC’s.
• x87 FADDs and FMULs are also handled by the FMAC.
• Each FMAC contains a variable latency divide/square root machine.
• Only 1 256-bit operation can issue per cycle, however an extra cycle can be incurred as in the case
of a FastPath Double if both micro ops cannot issue together.

The scheduler can receive and schedule up to four micro-ops (μops) in a dispatch group per cycle.
The scheduler tracks operand availability and dependency information as part of its task of issuing
μops to be executed. It also assures that older μops which have been waiting for operands are
executed in a timely manner. The scheduler also manages register mapping and renaming.

There are four integer execution units per core. Two units which handle all arithmetic, logical and
shift operations (EX). And two which handle address generation and simple ALU operations
(AGLU). This makes an Integer Cluster. There is two such clusters per compute unit.

Macro-ops are broken down into micro-ops in the schedulers. Micro-ops are executed when their
operands are available, either from the register file or result buses. Micro-ops from a single operation
can execute out-of-order. In addition, a particular integer pipe can execute two micro-ops from
different macro-ops (one in the ALU and one in the AGLU) at the same time. The scheduler can receive up to four macro-ops per cycle. This group of macro-ops is
called a dispatch group.

EX0 contains a variable latency non-pipelined integer divider. EX1 contains a pipelined integer
multiplier. The AGLUs contain a simple ALU to execute arithmetic and logical operations and
generate effective addresses. A load and store unit (LSU) reads and writes data to and from the L1
data cache. The integer scheduler sends a completion status to the ICU when the outstanding microops
for a given macro-op are executed.
The LZCNT and POPCNT operations are handled in a pipelined unit attached to EX0

Just some help

How is this NOT obvious to people still? Come on, they're pricing an Eight-Core, 3.1-4GHz CPU against a Quad-Core, 3.3-3.8GHz CPU. That should tell you everything, and that is that it has eight weak cores and to try and counter a bit for that deficit they ramp up the clock speeds. It also has a deeper pipeline than Sandy Bridge, to facilitate those higher clock speeds in the first place even if it means losing some IPC.

The only chance it has is in multi-threaded applications, as that's always where many parallel slow cores do better than lesser, faster ones. Even then, if IPC is low enough and they lose too much performance from the module concept, it wouldn't look very good. It makes more sense every time I look at it: Bulldozer was meant to be a server CPU first and foremost. Sandy Bridge makes more sense for desktop workloads.

IPC is static to the functional units....It can't go beyond them..(Clockrate doesn't affect IPC)

IPS is dynamic and heavily dependent on clockrates, prefetchs and predictions and in some apps cache(Clockrate does affect IPS)

 

[Dresdenboy]

It looks like at least one person here sees the BD pipeline a bit being too unflexible. But there are lots of buffers inbetween. Same for SB. E.g. if there are 6 execution ports to be fed, it is enough to find up to 6 uops ready for issueing them, no matter which thread they belong to. It also doesn't matter what uops get fed into the scheduler at the same cycle.

It's like an office. At each desk there are heaps of documents in the inbox and get processed with oldest first. If something is missing to process it, another one is taken first (out of order). If the office worker can do multiple docs at once, this is called superscalar. Then there is an expert for calculations (FPU) etc. Some guy prepares the next docs and accompanying information and directs finished docs to their reciepients (OoO L/S). Another one prepares and selects the work to be done according to what the upper management demanded (prefetch, decode). Since there are actually 2 demanding managers (threads) he (lets call him ?Front End?) has to manage resources and even guess the management's next wishes (branch prediction). There is a bit more to it but its easy to see that not every single stalled cycle somewhere will stall everything.

(This little story has been written while being on my way home )

 

[LOL_Wut_Axel]

Just some help



IPC is static to the functional units....It can't go beyond them..(Clockrate doesn't affect IPC)

IPS is dynamic and heavily dependent on clockrates, prefetchs and predictions and in some apps cache(Clockrate does affect IPS)

Having a deeper pipeline in a CPU design lowers IPC, but in most CPU designs also allows you to have higher clock speeds so you can raise single-threaded performance that way. I never mentioned clock speed affecting IPC; however, it does affect single-threaded performance.

 

[NostaSeronx]

Having a deeper pipeline in a CPU design lowers IPC,

Instructions per Cycle is very static(static in the sense that they can't excel beyond the functional units...amount of functional units limits IPC) and limited to the functional units(EX/AGLU), pipelines doesn't effect IPC but they do effect IPS.

An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time).

but in most CPU designs also allows you to have higher clock speeds so you can raise single-threaded performance that way.

IPS more instructions per second is always a good thing, whole point of overclocking

I never mentioned clock speed affecting IPC; however, it does affect single-threaded performance.

Having a deeper pipeline in a CPU design lowers IPC,

It also has a deeper pipeline than Sandy Bridge, to facilitate those higher clock speeds in the first place even if it means losing some IPC.

ILP improves with deeper pipelines, IPS improves do to the higher clocks as well

Just going to point this out

 

[LOL_Wut_Axel]

Instructions per Cycle is very static(static in the sense that they can't excel beyond the functional units...amount of functional units limits IPC) and limited to the functional units(EX/AGLU), pipelines doesn't effect IPC but they do effect IPS.



IPS more instructions per second is always a good thing, whole point of overclocking







ILP improves with deeper pipelines, IPS improves do to the higher clocks as well

Just going to point this out

My main point: take CPU A with XYZ architecture and take CPU B with XYZ architecture, and only differentiate between both by having CPU B having a deeper pipeline, and it'll have lower IPC than CPU A (though obviously how much will depend on other factors). Having a deeper pipeline can let you optimize for higher clock speeds as well, so if your architecture was already made for low IPC you're best served trying to clock your CPUs as high as you can. That's what Intel did with the Pentium 4.

Since it's pretty obvious that Bulldozer has much lower IPC than Sandy Bridge, that's why I mention it. AMD is trying to not bleed as much in single-threaded, so they clock them as high as they can. If it had decent IPC, it wouldn't need eight cores to compete with Intel's four to begin with.

 

[Zstream]

I don't care what anyone says. I need more cores for my VM farm

 

[Riek]

My main point: take CPU A with XYZ architecture and take CPU B with XYZ architecture, and only differentiate between both by having CPU B having a deeper pipeline, and it'll have lower IPC than CPU A (though obviously how much will depend on other factors). Having a deeper pipeline can let you optimize for higher clock speeds as well, so if your architecture was already made for low IPC you're best served trying to clock your CPUs as high as you can. That's what Intel did with the Pentium 4.

Since it's pretty obvious that Bulldozer has much lower IPC than Sandy Bridge, that's why I mention it. AMD is trying to not bleed as much in single-threaded, so they clock them as high as they can. If it had decent IPC, it wouldn't need eight cores to compete with Intel's four to begin with.

You are not talking about the same IPC.

He talks about the static theoretical IPC, you are talking about a derailed IPC of an application after the code has run. (i mention derlaied because you don't know the number of instructions it did and wether it is more or less in the program compared to others).

Deeper pipelines don't really affect theoretical ipc much. If nothing goes wrong (no certain branches) the deeper pipeline will only come a few cycles later in a good ooo environment.


I'm also not sure if we know for certain BD cores are that much weaker as you seem to imply. You have to see the core's with their design goals. So the core is running at higher frequencies, its the design goal. And i doubt SB will be 30% faster than BD in the uncommon and obsolete single threaded benchmark. When looking at the typical desktop workload between 2-4threads I don't see BD very far below SB (maybe 5-10%).

 

[NostaSeronx]

My main point: take CPU A with XYZ architecture and take CPU B with XYZ architecture, and only differentiate between both by having CPU B having a deeper pipeline, and it'll have lower IPC than CPU A (though obviously how much will depend on other factors). Having a deeper pipeline can let you optimize for higher clock speeds as well, so if your architecture was already made for low IPC you're best served trying to clock your CPUs as high as you can. That's what Intel did with the Pentium 4.

Since it's pretty obvious that Bulldozer has much lower IPC than Sandy Bridge, that's why I mention it. AMD is trying to not bleed as much in single-threaded, so they clock them as high as they can. If it had decent IPC, it wouldn't need eight cores to compete with Intel's four to begin with.

CPU A with XYZ architecture has higher IPC than CPU B with XYZ but CPU B can achieve much higher clocks on average

This new CPU B can also do micro/macro-op fusion(has been a CPU A thing since Core), has increased IPC over it's predecessor, has an increased complexity OoO engine(might be repeated), and other various things including.

• FP mov elimination
• full availability of shared ressources like the FPU to one thread if the other doesn't need them in one cycle
• the improved tournament prefetcher engines
• enhanced power management making better use of existing (measured) TDP headrooms for boosted P-States (instead of going with a heuristic rule like in Thuban)
• improved OoO capabilities (unified integer schedulers, improved L/S units)

and more deep dark Bulldozery secrets like the "secret options" in the BIOS and such

Also what is macro fusion or micro fusion?

This is it and it's finally in AMD CPUs(functionality in Bulldozer though is unknown)

http://www.anandtech.com/show/3863/amd-discloses-bobcat-bulldozer-architectures-at-hot-chips-2010/5
Shimpi I'm sorry I am repeating what you said already but oh well

 

[aigomorla]

OK who cares if zambini has 10000 threads...

and im not argueing with stability.

the machine can be 8ghz stable for all i care...

But what does a 8ghz BD machine translate into?
Because for sure hell it doesnt translate into a 8ghz PH2 machine on CB...

^ theres logic for you in why im mad.

 

[NostaSeronx]

the machine can be 8ghz stable for all i care...

But what does a 8ghz BD machine translate into?
Because for sure hell it doesnt translate into a 8ghz PH2 machine on CB...

8GHz translates to two times faster than 4GHz

The reason for Bulldozer having poor scores as far as I know is the delay and or the latency of the instructions for Phenom II it's X<12~ with a throughput of 1 or 2 in Bulldozer it has a latency of X>12 with a throughput of 1 or 2, if it's hardware based

Something like that

 

[Idontcare]

But what does a 8ghz BD machine translate into?
Because for sure hell it doesnt translate into a 8ghz PH2 machine on CB...

Since BD IPC > PhII IPC (per JFAMD), wouldn't an 8GHz BD > 8GHz PhII?

 

[aigomorla]

8GHz translates to two times faster than 4GHz

The reason for Bulldozer having as far as I know is the delay and or the latency of the instructions for Phenom II it's X<12~ with a throughput of 1 or 2 in Bulldozer it has a latency of X>12 with a throughput of 1 or 2

Here is my scenario..
and dont get me wrong..

I am going to be getting a new AMD machine for my friend to replace her old and aging X4 965.

Like most people who are interested in BD, we are contemplating do we migrate to a new platform, or do we upgrade the cpu.

So I, like most will be debating... X6 on the board.. or a BD or possible a low budget intel machine.

Now Intel machine will be great however its lacking cores the X6 machine has which my friend requires.

Intel 6 core is just out of the question, as i can build her 3 X6 machines for the cost of 1 intel 6 core.

What i was hoping to see was the BD being a "8core" cpu would trounce on a X6 @ clock to clock basis.

What we found out is... the 8 core machine is a AMD translation of 8cores, and doesnt clock ghz to ghz against an X6.

Now yes i know the X6 is a hexcore... and the BD is a quadcore... or u can call it an octocore... i personally dont care anymore at this point...

Forget 2600k vs BD... forget AMD vs INTEL entirely for a second... what i do care is... the X6 still looks like a more superior cpu over BD.

Or am i missing something???

Since BD IPC > PhII IPC (per JFAMD), wouldn't an 8GHz BD > 8GHz PhII?

and this is why i made my friend wait god knows how many months? only to hear another delay? and to see benchies where an X6 would stomp it?

You guys see why im so lost here and just annoyed?

 

[NostaSeronx]

what i do care is... the X6 still looks like a more superior cpu over BD.

--the Adds---Bulldozer
ADDPD_reg FMA[P0 | P1] FastPath Single 5
ADDPS_reg FMA[P0 | P1] FastPath Single 5
ADDSD_reg FMA[P0 | P1] FastPath Single 5
ADDSS_reg FMA[P0 | P1] FastPath Single 5
ADDSUBPD_reg FMA[P0 | P1] FastPath Single 5
ADDSUBPS_reg FMA[P0 | P1] FastPath Single 5

---the Muls---Bulldozer
MULPD_reg FMA[P0 | P1] FastPath Single 5
MULPS_reg FMA[P0 | P1] FastPath Single 5
MULSD_reg FMA[P0 | P1] FastPath Single 5
MULSS_reg FMA[P0 | P1] FastPath Single 5

---The Adds---Ph II
ADDPD xmmreg1, xmmreg2 (mem) DirectPath Single&#9733; FADD 4
ADDPS xmmreg1, xmmreg2 (mem) DirectPath Single&#9733; FADD 4
ADDSD xmmreg1, xmmreg2 (mem) DirectPath Single FADD 4
ADDSS xmmreg1, xmmreg2 (mem) DirectPath Single FADD 4
ADDSUBPD xmmreg1, xmmreg2 (mem) DirectPath Single&#9733; FADD 4
ADDSUBPS xmmreg1, xmmreg2 (mem) DirectPath Single&#9733; FADD 4

---The Muls---Ph II
MULPD xmmreg1, xmmreg2 (mem) DirectPath Single&#9733; FMUL 4
MULPS xmmreg1, xmmreg2 (mem) DirectPath Single &#9733; FMUL 4
MULSD xmmreg1, xmmreg2 (mem) DirectPath Single FMUL 4
MULSS xmmreg1, xmmreg2 (mem) DirectPath Single FMUL 4

I don't see how 1 cycle can blow everything up there are some cases where Bulldozer is 1 cycle faster to 2 cycles slower as well and in the mrom latency Bulldozer is faster in some areas as well(loads equal 10 for Bulldozer and 2 for Phenom II for FPU delays in this case Bulldozer goes to 15 and K10/K12 goes to 6)

 

[aigomorla]

I don't see how 1 cycle can blow everything up there are some cases where Bulldozer is 1 cycle faster to 2 cycles slower as well and in the mrom latency Bulldozer is faster in some areas as well

lol i know i totally see your point.

Paper spec wise its beautiful.
i cant argue with you guys on paper spec.

But from real life benching.. and as i said unless something is seriously wrong with the cpu...

if you look at cinebench, wprime... anything... the X6 @ clock is easily pacing it.
Now true u dont have the OC wall as a BD, but the X6 has 2 more "real cores" if u want to call them real or whatnot... they have 2 more of something that BD doesnt have, but an overall 2 threads less.

 

[NostaSeronx]

l
if you look at cinebench, wprime... anything... the X6 @ clock is easily pacing it.
Now true u dont have the OC wall as a BD, but the X6 has 2 more "real cores" if u want to call them real or whatnot... they have 2 more of something that BD doesnt have, but an overall 2 threads less.

I don't know I would wait for the release and benchmarks from those who we trust

 

[Phynaz]

I don't know I would wait for the release and benchmarks from those who we trust

Who do you trust?

 

[Arkadrel]

lol i know i totally see your point.

Paper spec wise its beautiful.
i cant argue with you guys on paper spec.

But from real life benching.. and as i said unless something is seriously wrong with the cpu...

if you look at cinebench, wprime... anything... the X6 @ clock is easily pacing it.
Now true u dont have the OC wall as a BD, but the X6 has 2 more "real cores" if u want to call them real or whatnot... they have 2 more of something that BD doesnt have, but an overall 2 threads less.

Theres a reason for that... most of them are most likely fakes, ment to grab attention (page hits for sites, that deal with rumors), or Intel trolls that think its funny makeing "news" about a underperforming Bulldozer (alla ORB).

Just wait until it launches, so you know your looking at the "real" thing, benchmarked by professionals, where everything is in working order.

Instead of most likely fakes + engineering samples (with crippled parts) + missing bios bla bla bla stuff ect.

How many threads about fake benchmarks are there so far? and guys admitting they made them up? like ORB.

Who do you trust?

Anandtech on launch date, when he benches it and puts a review up on the site, for one.

 

[aigomorla]

Anandtech on launch date, when he benches it and puts a review up on the site, for one.

and i think all of u guys have missed me saying...

ive seen the numbers at the invite to TX, when a bunch of people were invited to AMD at the event they broke the world record.
I know at least 4 of the people who were invited...

:\

OK...

But i see your point... lets wait for "real" benchmarks, because if that WR benchmark isnt considered real, we can tell HWBOT to remove it.

 

[statikregimen]

Did I miss something? Everybody is still talking like BD has been released and we have official, 3rd party benchmark results in hand