Samsung shows off 14nm FinFET wafers and systems

[oobydoobydoo]

I don't know if this has been posted here before, but according to this Samsung has already produced working ARM devices on 14nm FinFET

"Samsung’s 14nm FinFET technology process taped out multiple test chips ranging from a full ARM CortexTM-A7 processor implementation to a SRAM-based chip capable of operating near threshold voltage levels, as well as
an array of analog IP. "

http://www.samsung.com/global/business/semiconductor/file/media/Samsung_Foundry_14nm_FinFET-0.pdf

And in this article here, it's states that Samsung will be producing chips for Qualcomm, Apple, and AMD.

http://www.tomshardware.com/news/samsung-amd-qualcomm-apple-finfet,27808.html

It should be easy to see who the best ARM chip designer is if they all use the same 14nm Samsung process.

Of particular interest is this comment here, which contains a bit of information I haven't heard before: "This year, Apple is already using the 20nm process from both Samsung and TSMC, although it's only using Samsung's foundry for 30 percent of the A8 chips. According to ZDNet Korea's sources, it looks like Apple will use Samsung's foundry almost exclusively for the 14nm process next year."



Is A8X only behind Produced by TSMC? Either way, there should be examples of A8 or A8X from both Samsung and TSMC. Would it not be possible to do a perfect Apples to Apples (no pun intended) comparison between the two 20nm processes?

 

[krumme]

I'm curious...why do you refer to Qualcomm as "qq"?

Yeaa wtf. I dont know, at least i do it consistently. Lol.

 

[Arachnotronic]

Yeaa wtf. I dont know, at least i do it consistently. Lol.

Fair enough! Not a criticism, was just legitimately curious

 

[ShintaiDK]

I don't know if this has been posted here before, but according to this Samsung has already produced working ARM devices on 14nm FinFET

"Samsung’s 14nm FinFET technology process taped out multiple test chips ranging from a full ARM CortexTM-A7 processor implementation to a SRAM-based chip capable of operating near threshold voltage levels, as well as
an array of analog IP. "

Making a few chips is one thing, mass producing a whole other one. I am sure Intel got 10nm chips running today. They just cant mass produce them yet.

If I recall right the first 20nm test ARM chips was in 2011.

 

[witeken]

Making a few chips is one thing, mass producing a whole other one. I am sure Intel got 10nm chips running today. They just cant mass produce them yet.

They (very likely) even have 7nm chips.

 

[krumme]

They (very likely) even have 7nm chips.

Agree. And my guess is they have a qualified estimate of density and yield for final production. They know they can get acceptable results without euv.
We have to remember that doing so comes at the cost of a huge experienced staff of process specialist. Intel have cost that is viewed as more fixed cost where others foundries will take that as more variable cost. Gives good sense. Both approaches is right and fit the situation - eg Intel feeding the servermarket where they have near monopoly and can therefore eg plan for a 7-10 year development of inhouse expertise.

 

[Ajay]

They (very likely) even have 7nm chips.

IDC would know best, but I imagine that Intel is just running test shuttles with some sram and simple logic. The process must be highly variable right now in terms of structure and electrostatics. Plus, I'm guessing they are running multi-pattering as well as EUV trials (hoping the EUV works out).

 

[exar333]

http://semiaccurate.com/2010/10/18/amd-shows-llano-wafer/

:whiste:

 

[Idontcare]

They (very likely) even have 7nm chips.

IDC would know best, but I imagine that Intel is just running test shuttles with some sram and simple logic. The process must be highly variable right now in terms of structure and electrostatics. Plus, I'm guessing they are running multi-pattering as well as EUV trials (hoping the EUV works out).

7nm sram yes, but I don't know if it is on 450mm and 300mm or just 450mm at this juncture, yes to EUV.

 

[carop]

They (very likely) even have 7nm chips.

It is seems Intel has not yet decided what transistor options, materials and structures would be best for 7nm:

SE: At 7nm, the industry may need to go to a new transistor structure. The options include III-V finFETs, gate-all-around FETs, quantum well finFETs and SOI finFETs. Has Intel made a decision about its next-generation transistor technology yet?

Bohr: Our research group has cast a wide net in terms of what transistor options, materials and structures would be best for 7nm. We have not made that decision yet. Answering that question becomes an ever more complex problem. You not only want to make it smaller, and provide better performance, but it also has to have low capacitance and low leakage. It’s a tall set of requirements.

http://semiengineering.com/one-on-one-mark-bohr/

Crystalline germanium and III-V devices are possible solutions, but results reported at major conferences show either PMOS or NMOS devices, but not both together as required for a CMOS process.

If anyone makes a breakthrough in terms of new channel materials, it will be all over the Internet.

 

[III-V]

It is seems Intel has not yet decided what transistor options, materials and structures would be best for 7nm:



http://semiengineering.com/one-on-one-mark-bohr/

Crystalline germanium and III-V devices are possible solutions, but results reported at major conferences show either PMOS or NMOS devices, but not both together as required for a CMOS process.

If anyone makes a breakthrough in terms of new channel materials, it will be all over the Internet.

When such a breakthrough is published, sure. But not until then, except in the rather unlikely event of a leak. Intel's been much less open about things since BK took the reins, and now things are basically not disclosed until launch, or just before.

 

[witeken]

It is seems Intel has not yet decided what transistor options, materials and structures would be best for 7nm:

Crystalline germanium and III-V devices are possible solutions, but results reported at major conferences show either PMOS or NMOS devices, but not both together as required for a CMOS process.

If anyone makes a breakthrough in terms of new channel materials, it will be all over the Internet.

I would take these comments with a big grain of salt. For reference, Intel had already figured out 10nm at IDF 2012. We're now 2 IDFs (years) further and assuming they were still assuming this 2 year* Tick-Tock cadence for 7nm release deadline, then they should be close to figuring out 7nm by now.

As Brian Krzanich said** at Investor Meeting: Intel does not want to leak any information about its processes or release cadence, so we should not expect any answer. Unless 7nm somehow becomes a lot harder than all previous nodes, I expect 7nm to be a refinement (2nd generation) of the technology they introduce at 10nm. Also note that the pathfinding length of these technologies is immense, up to a decade. For example, Intel started FinFET research in 2001. They were making progress: first single fin devices, then multiple fin devices, then some early SRAM cells, and in 2008 they made the decision and became fully committed for the 22nm FF technology, because planar was not enough anymore, so about 3-4 years from full commitment to HVM-products. (http://spectrum.ieee.org/tech-talk/semiconductors/devices/getting-beyond-darn-good-devices)

* Source: “So if we were actually executing to our 2 year beat rate, then those [22 and 14nm] [yield] lines should have been on top of each other, and clearly they're not.” --William Holt

** Quote: “We felt like we went on a little early with 14nm as far as timing and performance and features and we saw actually competitors adjust to that. So we're gonna be a little bit more prudent, a little smarter about signalling to the industry exactly when, what and where. And you'll have to trust a little bit the 50 year history we have with Moore's Law and that we should be able to keep it going for 51 or 52 years. So we're gonna be a little careful there about that signalling exactly when, what and where.” --Brian Krzanich, CEO Intel

Edit: great interview, thanks.

 

[NTMBK]

Unless 7nm somehow becomes a lot harder than all previous nodes, I expect 7nm to be a refinement (2nd generation) of the technology they introduce at 10nm.

Given that we're racing headlong towards the nanoscale wall... I would be surprised if 7nm wasn't a lot harder.

 

[witeken]

Given that we're racing headlong towards the nanoscale wall... I would be surprised if 7nm wasn't a lot harder.

I mean if the amount of improvements somehow starts to become much harder that we need say Ge and III-V at 10, GAA and nanowire at 7, tunneling transistor at 5, CNT at 3, spintronics at 2, silicene at 1, graphene at 0.7, superconductivity at 0.5 and quantum computing at 0.35 instead of using each of those innovations for 2 nodes. On the other hand, how many shrinks are left? If we hit Moore's Wall at say 2, then they can only introduce new technologies without any transistor density increases from silicene on. But those semiconductor people seem ridiculously smart, so we'll see.

 

[Idontcare]

Given that we're racing headlong towards the nanoscale wall... I would be surprised if 7nm wasn't a lot harder.

Not harder, just more expensive.

"Harder" implies difficulty, and it isn't difficult to shrink things. But it is hard to shrink things if you don't have the money, if you can't afford to do the work necessary to shrink things.

It was not hard for the USA to put some people on the moon, but it was expensive. Too expensive for just about every other country on the planet at the time, so we got to be the first and only nation to do it. Not for our technical prowess but for our willingness as a nation to invest our resources into that single-minded goal at the expense of investing those same resources into other projects (e.g. improving the sciences related to mental health of troubled children who may have easy access to firearms, etc.).

I've been through many node shrinks, and none of them were technologically problematic. But all of them were bound by economics, our development budgets determined the scope of the node shrink (targeted electric and areal parametrics) and we as process development engineers merely worked (not slaved, not busted our brains, but simply worked at our job day after day) to meet key project milestones on a timely basis.

The only time things got painful was when someone would drop the ball and hold up the rest of the team. An etch process might not get optimized in time to enable yield milestone XYZ but the CMP and Cu fill processes did. Then you shuffle resources (wafers, engineers, etc) around so the weakest link gets the attention it needs. But again that was always a personnel driven thing (weakest link == weakest engineer) and not a technology driven thing (weakest line != weakest toolset).

But it is true that you sometimes get a management situation where managers think you can get something for nothing, blood from a stone, and they set absolutely unrealistic project scopes (in time and deliverables) with respect to the budget. The guy who says "we're going to put a man on the moon in 3 years and only spend $5 doing it!"

In that case you have just made things "hard" for the engineers because they are now expected to be magicians, not at science but at economics.

And in many ways that is kinda where today's foundries are sitting, a few of them that I know of are way under-budgeted with respect to the publicized ambitions of their executive decision makers, and no surprise that they continue to fail to deliver on those lofty timelines and deliverables.

7nm will be a lot more expensive to develop, but not any harder than developing 10nm unless some unlucky company is being ran by an individual or two who thinks 7nm ought to be developed with the same budget as 65nm required.

 

[jdubs03]

I'm not surprised that Bohr would downplay the materials and transistor structure for 7nm, mainly because even though there isn't much on 10nm, 7nm is not too far off into the future. I'm sure at D1X and the new module those R&D labs have 7nm and probably 5nm transistors switching, just on an increasingly smaller scale.

From the interview:

SE: Some say the III-V materials have been pushed out or delayed. Any thoughts on that?

Bohr: Other companies may choose to push out the adoption of III-V, because all of the problems have not been solved for the 10nm generation. Tool readiness doesn’t seem to be the issue. It’s mostly device physics.

Intel has already determined 10nm, has the tools already; so when Bohr says "other companies" he could be excluding Intel, at least from that response it seems plausible as they have a good handle on 10nm at this stage. On a counterpoint, because the device scaling for the foundries is behind Intel, and Intel's 10nm is aligned with the foundries 7nm, maybe Intel will wait to 7nm for III-V.

 

[carop]

pMOS channels can be easily made with germanium (Ge). Forming n-junctions in Ge is inherently difficult. So, there is R&D competition to form the nMOS channel:

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

http://semimd.com/blog/2014/11/25/germanium-junctions-for-cmos/

 

[NTMBK]

Not harder, just more expensive.

"Harder" implies difficulty, and it isn't difficult to shrink things. But it is hard to shrink things if you don't have the money, if you can't afford to do the work necessary to shrink things.

It was not hard for the USA to put some people on the moon, but it was expensive. Too expensive for just about every other country on the planet at the time, so we got to be the first and only nation to do it. Not for our technical prowess but for our willingness as a nation to invest our resources into that single-minded goal at the expense of investing those same resources into other projects (e.g. improving the sciences related to mental health of troubled children who may have easy access to firearms, etc.).

I've been through many node shrinks, and none of them were technologically problematic. But all of them were bound by economics, our development budgets determined the scope of the node shrink (targeted electric and areal parametrics) and we as process development engineers merely worked (not slaved, not busted our brains, but simply worked at our job day after day) to meet key project milestones on a timely basis.

The only time things got painful was when someone would drop the ball and hold up the rest of the team. An etch process might not get optimized in time to enable yield milestone XYZ but the CMP and Cu fill processes did. Then you shuffle resources (wafers, engineers, etc) around so the weakest link gets the attention it needs. But again that was always a personnel driven thing (weakest link == weakest engineer) and not a technology driven thing (weakest line != weakest toolset).

But it is true that you sometimes get a management situation where managers think you can get something for nothing, blood from a stone, and they set absolutely unrealistic project scopes (in time and deliverables) with respect to the budget. The guy who says "we're going to put a man on the moon in 3 years and only spend $5 doing it!"

In that case you have just made things "hard" for the engineers because they are now expected to be magicians, not at science but at economics.

And in many ways that is kinda where today's foundries are sitting, a few of them that I know of are way under-budgeted with respect to the publicized ambitions of their executive decision makers, and no surprise that they continue to fail to deliver on those lofty timelines and deliverables.

7nm will be a lot more expensive to develop, but not any harder than developing 10nm unless some unlucky company is being ran by an individual or two who thinks 7nm ought to be developed with the same budget as 65nm required.

Interesting, thanks IDC :thumbsup: Out of curiousity, what is the main driver for that increasing cost? Increased headcount?

 

[witeken]

Not harder, just more expensive.

I've been through many node shrinks, and none of them were technologically problematic. But all of them were bound by economics, our development budgets determined the scope of the node shrink (targeted electric and areal parametrics) and we as process development engineers merely worked (not slaved, not busted our brains, but simply worked at our job day after day) to meet key project milestones on a timely basis.

7nm will be a lot more expensive to develop, but not any harder than developing 10nm unless some unlucky company is being ran by an individual or two who thinks 7nm ought to be developed with the same budget as 65nm required.

Surely it becomes harder, not only more expensive: Intel does not have even the slightest financial problems, yet they failed horribly (not just slightly) to deliver 14nm within Intel's 2 year beatrate. That is, sort of by definition, what harder means.

 

[witeken]

Intel has already determined 10nm, has the tools already; so when Bohr says "other companies" he could be excluding Intel, at least from that response it seems plausible as they have a good handle on 10nm at this stage. On a counterpoint, because the device scaling for the foundries is behind Intel, and Intel's 10nm is aligned with the foundries 7nm, maybe Intel will wait to 7nm for III-V.

They won't. See my signature:

 

[jdubs03]

They won't. See my signature:

When looking at all of the pieces I would imagine 10nm is their next-gen innovation with 7nm being a refinement of that, but for sure that is not certain. I guess we'll find out next fall.

 

[NostaSeronx]

I've been finding notions that Samsung's FinFETs will not be on time.

While, TSMC and Intel are validated up to 12 metal stacks and up. Samsung and GlobalFoundries are validated up to 8 metal stacks and down. (This includes 20nm-LPM/20-nm LPP, hence why Apple moved to TSMC to get 10 metal stacks.)

There is also an issue with the tools both Samsung and GlobalFoundries use. The issue wouldn't be disclosed, but it is impacting the Fin etch. Implying, that it is deleting Fins that shouldn't be deleted.

Samsung Libs;
10.5 Track (LPP)
9 Track (LPP)
9 Track (LPP/LPe)

Samsung Metal layers supported;
Metal stacks up to 8 layers.

At this point, Intel's true 14-nm FinFETs are having higher yields. Than, 20nm and FinFETs at Samsung/GlobalFoundries.

 

[witeken]

When looking at all of the pieces I would imagine 10nm is their next-gen innovation with 7nm being a refinement of that, but for sure that is not certain. I guess we'll find out next fall.

I doubt it. I think the 3 year cycle will become widespread. After 2015 we will have Skylake-K and Skylake-Y/U/M/E, and maybe Skylake refresh called Icelake. 10nm will ramp in H2'16, so I guess we'll find out at IDF16.

 

[witeken]

I've been finding notions that Samsung's FinFETs will not be on time.

While, TSMC and Intel are validated up to 12 metal stacks and up. Samsung and GlobalFoundries are validated up to 8 metal stacks and down. (This includes 20nm-LPM/20-nm LPP, hence why Apple moved to TSMC to get 10 metal stacks.)

There is also an issue with the tools both Samsung and GlobalFoundries use. The issue wouldn't be disclosed, but it is impacting the Fin etch. Implying, that it is deleting Fins that shouldn't be deleted.

Samsung Libs;
10.5 Track (LPP)
9 Track (LPP)
9 Track (LPP/LPe)

Samsung Metal layers supported;
Metal stacks up to 8 layers.

At this point, Intel's true 14-nm FinFETs are having higher yields. Than, 20nm and FinFETs at Samsung/GlobalFoundries.

How do you know all these things?

 

[NostaSeronx]

How do you know all these things?

A "couple" of people will be axed soon.

The whole PR hush thing by Samsung/GlobalFoundries/AMD and a couple others are pretty condemning.