SAM/GF 14LPP promisses 75% less area and 2-4 times less power versus 28nm processes

[witeken]

but 10 nm is really exciting too.

Intel's 10nm will be, if they deliver.

On SemiEngineering, I read a lot of things about SiGe and III-V potentially delayed, so maybe Intel's 10nn won't be matched until 5nm.

 

[ThatBuzzkiller]

That's 4x the die scaling or I would like to say but their probably fudging some of the numbers however, I'm nonetheless impressed by how much their focusing on that aspect!

This certainly confirms that Apple can't be using TSMC's 16nm process to produce their A9's or even the A9X otherwise it would be next to impossible for TSMC to hit those performance targets at a reasonable budget ...

 

[Arachnotronic]

That's 4x the die scaling or I would like to say but their probably fudging some of the numbers however, I'm nonetheless impressed by how much their focusing on that aspect!

This certainly confirms that Apple can't be using TSMC's 16nm process to produce their A9's or even the A9X otherwise it would be next to impossible for TSMC to hit those performance targets at a reasonable budget ...

Except somebody on these very forums with knowledge of the situation has flat out told us that TSMC will be building the A9.

 

[ThatBuzzkiller]

Except somebody on these very forums with knowledge of the situation has flat out told us that TSMC will be building the A9.

Hmm ...

Hasn't shipped any silicon with FinFET transistors yet ...

Expects "very small" revenue contribution from 16nm in Q3 ...

Inferior transistor characteristics ...

Sure they are making Apple A9's ...

 

[Arachnotronic]

Hmm ...

Hasn't shipped any silicon with FinFET transistors yet ...

Expects "very small" revenue contribution from 16nm in Q3 ...

Inferior transistor characteristics ...

Sure they are making Apple A9's ...

Proof that 16FF+ has "inferior transistor characteristics"?

 

[cbn]

It's a shame really, because I think there's a hole so big on the low end that AMD could drive a truck through it. Not that I'm suggesting that AMD can or would make a big splash in the phone or tablet markets . . . more like the cheap-arsed AiO market, and all the other strange places that Jaguars and Bay Trails wind up where they really shouldn't.

I think there is also a huge hole in the low end dGPU market (re: We are in a time of surplus SFF corporate desktops that when repurposed for consumer duty could use something better than Intel GMA or Intel HD graphics from LGA 1156 or LGA 1155 era).

This GF 14nm would probably be great for making sub 40W dGPUs to fit that need.

 

[ThatBuzzkiller]

Proof that 16FF+ has "inferior transistor characteristics"?

http://globalfoundries.com/docs/def...dries-14nm-collaboration---final.pdf?sfvrsn=2

Samsung's 14nm transistor claims 15% better die area scaling than "other foundries" 20nm transistors (TSMC) ...

There's a reason why TSMC got dumped by Apple and won't be returning to them until at least 2017 (14nm LPP) ...

 

[beginner99]

Double the efficiency and that likely includes uArch enhancements.

Yeah and probably also a steep price increase. Not to mention yields will never ever be as good as on 28nm so GPUs will become smaller and the actual performance increase from 28nm flagship to first 14nm versions hence will be even lower, maybe 30% albeit at much lower power usage.

 

[witeken]

Proof that 16FF+ has "inferior transistor characteristics"?

http://www.extremetech.com/wp-content/uploads/2014/12/Cell-SizeComparison.png

1.15x lower density.

Further, who says it's FinFET+? It should be FF.

 

[sm625]

14nm is two full nodes after 28nm. Just like 65nm was 2 full nodes after 130nm. When you add architectural advancements as well as finfet, 1/4 power consumption is a very reasonable target. Just compare a 130nm northwood to a 65nm conroe. That was 1/4 the power consumption for the same performance. Hell, it was probably better than that. You could literally run two 65nm conroe cores at the lowest possible frequency and voltage, and its performance would be greater than a 3.2GHz northwood. Also, the timespan is about the same in each case as well. The 3.2GHz P4 was launched in mid 2003, and conroe 3 years later. The first 28nm smartphone SoCs were launched 3 years ago. It all fits well within expectations of a full 2 node jump.

 

[AtenRa]

14nm is two full nodes after 28nm. Just like 65nm was 2 full nodes after 130nm. When you add architectural advancements as well as finfet, 1/4 power consumption is a very reasonable target. Just compare a 130nm northwood to a 65nm conroe. That was 1/4 the power consumption for the same performance. Hell, it was probably better than that. You could literally run two 65nm conroe cores at the lowest possible frequency and voltage, and its performance would be greater than a 3.2GHz northwood. Also, the timespan is about the same in each case as well. The 3.2GHz P4 was launched in mid 2003, and conroe 3 years later. The first 28nm smartphone SoCs were launched 3 years ago. It all fits well within expectations of a full 2 node jump.

The electrical properties are 2 full nodes apart from 28nm planar, perhaps a little more due to finfets. In the case of GloFo, we may even get more because 28nm is Gate First when 14nm will be Gate Last.

The density is 1.5 nodes vs 28nm planar.

 

[witeken]

The electrical properties are 2 full nodes apart from 28nm planar, perhaps a little more

Lol no. 20nm was an abomination and for sure a regression in terms of leakage, so that's 1.5 nodes at most.

The density is 1.5 nodes vs 28nm planar.

28->20nm was 1.9x, which is barely one Moore's Law node. FinFET uses the same BEOL.

 

[AtenRa]

Lol no. 20nm was an abomination and for sure a regression in terms of leakage, so that's 1.5 nodes at most.

Where did you see that ???

28->20nm was 1.9x, which is barely one Moore's Law node. FinFET uses the same BEOL.

Since you get an extra density going to FF we count it as a half node.

 

[ThatBuzzkiller]

Since you get an extra density going to FF we count it as a half node.

Not true ...

Going to FinFETs only change transistor structure, not it's density scaling ...

 

[AtenRa]

Not true ...

Going to FinFETs only change transistor structure, not it's density scaling ...

You can get 10-15% higher density due to the difference in the physical structure of the FinFet transistor vs bulk and secondly because you can do the same job using less transistors due to higher performance of the FinFet transistor vs bulk.

 

[ThatBuzzkiller]

You can get 10-15% higher density due to the difference in the physical structure of the FinFet transistor vs bulk and secondly because you can do the same job using less transistors due to higher performance of the FinFet transistor vs bulk.

1. Density scaling is entirely dependent upon the distance of the half-pitch, not the transistor technology employed ...

2. The statement that you are making about using less transistors is pure TSMC damage control ...