SAM/GF 14LPP promisses 75% less area and 2-4 times less power versus 28nm processes

[el etro]

Ready for volume production and products shipping latter this year. Data at 37"05 mins here: https://youtu.be/SPQvgzL_DSc?t=2209

Up to 2.5 times the speed or Up to 90% more dynamic power, and up to 4-8 times less leakage.


I know this is just a presentation, but set the expectations high for the 14LPP performance.



How do you guys think about it? Will it be ready for AMD ZEN/Greenland and Nvidia Pascal in 2H 2016? IMO Yes. AMD needs so much it(for Zen), Nvidia needs it too in order to push Tegra systems...

The process is less suited for high performance processors, but will rock at mobile(or maybe even notebook) space.

 

[AtenRa]

Nice thanks,

Hell, even porting Kaveri to 14nm LPP without any mArchitectural enhancements will make it better than Broadwell (especially mobile).

ZEN Desktop/Server and ZEN APUs at least will have the right node process, lets see what they can do with it and all the IP they got so far.

 

[ShintaiDK]

Not going to happen.

Expect the benefits as it was going roughly a full node.

And you are certainly not getting 2-4x less power consumption.

Remember this?
http://www.geek.com/mobile/20nm-arm-processors-to-hit-3ghz-next-year-1561514/

Also one just have to compare Samsungs own chips at 28, 20 and 14nm to see what to expect.

 

[R0H1T]

Not going to happen.

Expect the benefits as it was going roughly a full node.

And you are certainly not getting 2-4x less power consumption.

Remember this?
http://www.geek.com/mobile/20nm-arm-processors-to-hit-3ghz-next-year-1561514/

Also one just have to compare Samsungs own chips at 28, 20 and 14nm to see what to expect.

This might just be one of those "up to" conditional statements that you often see, even from Intel for instance, also with uarch changes it is very much possible.

 

[mrmt]

This might just be one of those "up to" conditional statements that you often see, even from Intel for instance, also with uarch changes it is very much possible.

... and on the latest news the powerpoint foundry keeps up churning out more powerpoint slides.

 

[R0H1T]

... and on the latest news the powerpoint foundry keeps up churning out more powerpoint slides.

At the end of the day they have to sell the foundry, not literally of course, don't they

It's just like Apple, except here the customers will be more informed.

 

[mrmt]

At the end of the day they have to sell the foundry, not literally of course, don't they

It's just like Apple, except here the customers will be more informed.

Usually in the foundry business rock solid, timely, high volume, high yields execution trumps powerpoint slides every day of the week.

 

[R0H1T]

Usually in the foundry business rock solid, timely, high volume, high yields execution trumps powerpoint slides every day of the week.

I think the work they did with the Exynos 7xxx in the Galaxy s6's proves that they can do all of that, also the A9 later in the year, what remains to be seen however is whether they can achieve the same milestones with bigger, hotter, badder (more complex) chip designs

 

[mrmt]

I think the work they did with the Exynos 7xxx in the Galaxy s6's proves that they can do all of that, also the A9 later in the year, what remains to be seen however is whether they can achieve the same milestones with bigger, hotter, badder (more complex) chip designs

The slide wasn't from Samsung, but from Globalfoundries.

 

[R0H1T]

The slide wasn't from Samsung, but from Globalfoundries.

Aren't they basically using the same (fab) tech, from IBM nonetheless :\

IIRC someone on the forum said that Apple made them do this, for their A9, & so I expect closer cooperation between the two & very little difference between them going forward, certainly on 14nm.

 

[Idontcare]

I think the work they did with the Exynos 7xxx in the Galaxy s6's proves that they can do all of that, also the A9 later in the year, what remains to be seen however is whether they can achieve the same milestones with bigger, hotter, badder (more complex) chip designs

See any reference to 14nm LPE on that marketing slide?

 

[R0H1T]

See any reference to 14nm LPE on that marketing slide?

Nope, my bad I just looked at the title & didn't give much attention to the actual (marketing?) slide D:

Regardless of that I do believe some of those "up to" scenarios will come true, wrt power & perf.

 

[AtenRa]

Not going to happen.

Expect the benefits as it was going roughly a full node.

And you are certainly not getting 2-4x less power consumption.

Remember this?
http://www.geek.com/mobile/20nm-arm-processors-to-hit-3ghz-next-year-1561514/

Also one just have to compare Samsungs own chips at 28, 20 and 14nm to see what to expect.

The slide says 2x speed, 72% reduction in die area and 85% leakage reduction over 28nm HPP Planar.

https://youtu.be/SPQvgzL_DSc?t=2228

Why do you believe that is not possible ??? That is almost what you would have going from 28nm planar to 20nm FD-SOI.

 

[erunion]

Amd said its 14nm gpu would have double the efficiency of 28nm(Fiji?).
That should give everyone an idea of what 14LPP will offer.

 

[frozentundra123456]

Yea, I think 2x power efficiency is within the realm of possibility, but that 4x range seems totally unrealistic. But 2x power efficiency with a new architecture with improved ipc could make them a lot more competitive. What kind of clocks they can attain that efficiency at, is the big question, I think.

 

[Arachnotronic]

Amd said its 14nm gpu would have double the efficiency of 28nm(Fiji?).
That should give everyone an idea of what 14LPP will offer.

Double the efficiency and that likely includes uArch enhancements. Process-related efficiency gain is likely less.

 

[el etro]

Yea, I think 2x power efficiency is within the realm of possibility, but that 4x range seems totally unrealistic. But 2x power efficiency with a new architecture with improved ipc could make them a lot more competitive. What kind of clocks they can attain that efficiency at, is the big question, I think.

14nm is pratically one and half node shrink against 28nm processes.

 

[erunion]

Double the efficiency and that likely includes uArch enhancements. Process-related efficiency gain is likely less.

Right. Though I get the feeling that architecture improvements are minimal and that the gain is due to process.

 

[krumme]

Can anyone dissect anything meaningfull new information from such material?
If so - who and what?
If not - what is the purpose then?

 

[frozentundra123456]

14nm is pratically one and half node shrink against 28nm processes.

And your point is? You think 1.5 node shrinkage gives 4x lower power consumption?

 

[AtenRa]

Can anyone dissect anything meaningfull new information from such material?
If so - who and what?
If not - what is the purpose then?

Take 45W TDP Kaveri, keep the performance, reduce TDP to 15W, reduce the die size by ~60% and you have a 14nm FF Kaveri.

Now take the 45W TDP Kaveri performance and compare it to 15W TDP Broadwell.

That will give you a rough estimate.

 

[AtenRa]

And your point is? You think 1.5 node shrinkage gives 4x lower power consumption?

Where does it say about 4x power reduction ??

 

[el etro]

And your point is? You think 1.5 node shrinkage gives 4x lower power consumption?

Up to 4x in some operations. Overall is 75% reduction(Promissed on the silde...).

 

[el etro]

This node(14LPP) will not be ready this year, but in 2016 will be running at full capacity with very good yelds. I expect 2H16 for 14LPP products (made by AMD or by Nvidia) hit the market.

 

[Idontcare]

14nm is pratically one and half node shrink against 28nm processes.

Actually there is a lot of truth to this assertion because we have to consider the specific 28nm process that we are comparing the 14nm in regards to.

GF's 28nm is a gate-first process. Gate-first processes have intrinsically lower drive currents (for normalized gate width and operating voltage). Which means you have to crank up the voltage, and the leakage, as well as the transistor widths, and the die size, to hit your target operating clockspeeds in comparison to a gate-last 28nm the likes of TSMC's.

So, in going from a gate-first 28nm process to a finfet 14nm process, I would agree that some electrical parametrics are going to benefit in a seemingly super-linear fashion versus that of your standard node progression.