Ryzen: Strictly technical

[iBoMbY]

How many times does it have to be repeated? GloFo doesn't do LPU, and GloFo will always remain the main factory for AMD CPUs, as long as there is a WSA. It is highly unlikely that AMD will manufacture any CPUs at a secondary manufacturer (or any chip at two different manufacturers at the same time, because it would double a lot of fixed costs), and using a different process at this secondary manufacturer is even more unlikely.

 

[T1beriu]

GloFo doesn't do LPU

Corect. They have not announced LPU or any other improvement that Samsung has done to 14nm.

It is highly unlikely that AMD will manufacture any CPUs at a secondary manufacturer (or any chip at two different manufacturers at the same time, because it would double a lot of fixed costs

They changed the WSA to use other foundries. I think they did it as a backup in case the demand is very high and GF can't sustain it.

If they're using Samsung I'm sure they will use it for high margin products to cover the expenses of WSA.

using a different process at this secondary manufacturer is even more unlikely

Again, it depends. If the changes are very minor I think it can be done, if not, I agree.

 

[SpaceBeer]

IIRC, accoridng to latest WSA, AMD would have to pay penalties to GloFo only if they don't order certain number of wafers. So if GloFo is fully utilized, and AMD needs more chips, they can go to Samsung or TSMC without any consequences.

Regarding differences between Samsung's LPU, and GF's LPP, I don't think is huge enough in terms of manufacturing requirements, and it wouldn't be that hard (expensive) for AMD to use it for Zen. But also, Polaris refresh is using improved LPP, and it may be that one is quite similar to LPU, just GF didn't change the name 🙂

 

[The Stilt]

Is the 14nm LPU even available in volume at the moment?
AFAIK the node used for Polaris refreshes is 14nm LPC (i.e. more cost effective and more mature LPP).

 

[iBoMbY]

They changed the WSA to use other foundries. I think they did it as a backup in case the demand is very high and GF can't sustain it.

GloFo still needs to approve everything outsourced, and they won't approve them losing their bread and butter products.

 

[raghu78]

Is the 14nm LPU even available in volume at the moment?
AFAIK the node used for Polaris refreshes is 14nm LPC (i.e. more cost effective and more mature LPP).

14 LPU is not in production. 14 LPU PDKs are only now available. Any chip designed on 14 LPU can launch only in mid-H2 2018.

Sent from my SM-G935V using Tapatalk

 

[Ajay]

14 LPU is not in production. 14 LPU PDKs are only now available. Any chip designed on 14 LPU can launch only in mid-H2 2018.

Sent from my SM-G935V using Tapatalk

Thanks. Any links on this? I'm having a hard time figuring out what 14LPP+ is for GloFo. It could be similar to what what Intel has done (mainly, geometry change to the FinFet).
Anyway, haven't been able to find anything on 14LPP+ via Google. Maybe my google-fu sucks.

 

[maddie]

GloFo still needs to approve everything outsourced, and they won't approve them losing their bread and butter products.

Are you stating that even if GloFlo can't produce a product because of capacity constraints, AMD still has to get permission to fab elsewhere?

 

[moinmoin]

In the Q&A from the last AMD Financial Analyst Day Lisa Su stated that for 7nm they are working with both GloFo and TSMC.
https://www.techpowerup.com/233389/amd-to-continue-working-with-tsmc-globalfoundries-on-7-nm-ryzen

 

[scannall]

Are you stating that even if GloFlo can't produce a product because of capacity constraints, AMD still has to get permission to fab elsewhere?

Yes. It's the last nasty leftover from Hector. Hector benefited greatly. And came close to sinking the company.

 

[Veradun]

Is the 14nm LPU even available in volume at the moment?
AFAIK the node used for Polaris refreshes is 14nm LPC (i.e. more cost effective and more mature LPP).

PDK should be out now, so the answer should be "no".

Process design kits (PDK) for 14LPU and 10LPU process technologies will be available during the second quarter of 2017.

https://news.samsung.com/global/sam...ndry-offerings-with-14lpu-and-10lpu-processes

Yes. It's the last nasty leftover from Hector. Hector benefited greatly. And came close to sinking the company.

Hector Ruin

 

[CatMerc]

Is the 14nm LPU even available in volume at the moment?
AFAIK the node used for Polaris refreshes is 14nm LPC (i.e. more cost effective and more mature LPP).

Apparently not, it's still LPP.
I had the suspicion, but it was confirmed somewhere to be a more mature LPP.

 

[The Stilt]

Apparently not, it's still LPP.
I had the suspicion, but it was confirmed somewhere to be a more mature LPP.

The 14nm LPP is officially advertized as "2nd gen.".
Since the Polaris refreshes are advertized to be built with "3rd gen finfet process" it means either GF is tinkering with the process themselves, or 14nm LPC is used.
More mature production with the same exact process wouldn't justify it being called as newer generation.

 

[CatMerc]

The 14nm LPP is officially advertized as "2nd gen.".
Since the Polaris refreshes are advertized to be built with "3rd gen finfet process" it means either GF is tinkering with the process themselves, or 14nm LPC is used.
More mature production with the same exact process wouldn't justify it being called as newer generation.

That was my thought process too, but apparently AMD marketing thinks otherwise.

http://www.anandtech.com/show/11280/amd-announces-the-radeon-rx-500-series-polaris

Meanwhile on the manufacturing front, all of the revised Polaris chips are being manufactured on what AMD is calling the “Latest Generation FinFET 14” process. This is a bit of a mouthful, but in short it’s AMD calling attention to the improvements partners GlobalFoundries and Samsung have made to their 14nm LPP processes in the last year. Yields are up and overall chip quality is better, which improves the average performance (clockspeed & power) characteristics of the chips. Both foundries have also been making other undisclosed, small tweaks to their lines to further boost chip quality.

 

[fleshconsumed]

Curious, would it be technically possible to hav more than 8 cores on AM4 platform? Are there enough pins to have more than 8 cores? Just wondering if Zen2 could have more than 8 cores when it comes a year or two later? Does anybody know?

 

[teejee]

Curious, would it be technically possible to hav more than 8 cores on AM4 platform? Are there enough pins to have more than 8 cores? Just wondering if Zen2 could have more than 8 cores when it comes a year or two later? Does anybody know?

well, it would still be with dual channel memory though. No pins on AM4 for quad channel.
I don't think dual channel on 12 or 16 core is acceptable.

Sent from my LG-D855 using Tapatalk

 

[DrMrLordX]

Probably not acceptable for 16 core unless there are some major improvements in DDR4 speeds (and an IMC to match). DDR4-4266 would be a minimum!

 

[The Stilt]

Probably not acceptable for 16 core unless there are some major improvements in DDR4 speeds (and an IMC to match). DDR4-4266 would be a minimum!

Having two dies in MCM wouldn't change the bandwidth (MEMCLK) requirement, since the inter-die communication takes place on GMI.

 

[Opcode]

Curious, would it be technically possible to hav more than 8 cores on AM4 platform? Are there enough pins to have more than 8 cores? Just wondering if Zen2 could have more than 8 cores when it comes a year or two later? Does anybody know?

There's a limited number of pins on AM4. Future products will likely have the same integrated I/O capabilities. Eight cores on AM4 (what is really a mainstream platform) I think is plenty for the next several years. All AMD needs to do is commit to IPC increases while maintaining the same or less power. Any clock improvements would only be a bonus. That seems to be AMD's forward focus is IPC improvements.

 

[coercitiv]

Eight cores on AM4 (what is really a mainstream platform) I think is plenty for the next several years.

Indeed, eight cores is plenty for the life of AM4: frequency increase alone could keep this platform afloat, considering we're talking about 25% headroom in (MT) clocks as manufacturing process improves and power usage allows. Add any IPC jump on top of that, even if we stay in the realm of 5-10%, and there's plenty of room to grow as efficiency rises, likely more than next gen process allows for.

 

[Timur Born]

I am sure someone is interested in this. Edit "L2 to L2" to "Remote L2", sorry for the confusion.

Interestingly remote L2 cache hit latency is slightly higher one way around (CPU0 to CPU10) than the other way around (CPU10 to CPU0).

 

[tamz_msc]

Is anybody aware of the issues with Ryzen throwing up random segfaults during heavy-duty compilation tasks and the associated thread over @ Gentoo forums?

 

[Timur Born]

Someone correct me please, but after comparing 3333-14 vs. 3600-18 it seems that lower latency memory is bottlenecked by the (whatever) fabric connection between CPU and memory? I would expect 3333-14 latency to be lower than 3600-18, but alas, it is not so.

 

[CatMerc]

Someone correct me please, but after comparing 3333-14 vs. 3600-18 it seems that lower latency memory is bottlenecked by the (whatever) fabric connection between CPU and memory? I would expect 3333-14 latency to be lower than 3600-18, but alas, it is not so.

Any number of factors could be affecting it. Don't forget the various subtimings.

 

[Timur Born]

I am running tighter sub-timings with 3333-14, so that should be covered, other than the impact on latency being miniscule. Most of the other factors should be under my control as well.

It really seems that tightening 3333-14 any further has little impact, while running 3600 much looser wins the latency race. I interpret this as the (whatever) fabric being the bottleneck with the lower memory clock rate (MT/2). But other people with more insight might be able to clarify this?!