Ryzen: Strictly technical

[Timur Born]

Just yesterday it dawned on me that in all the dynamic offset and sense skewing mess I missed something. And indeed I did, namely: when Sense Skew is disabled my Tctl is around 40 C, while the CPU socket sensor is around 23 C and ambient about 21 C. This is at full idle, stock CPU with cores clocked down and running at ultra-low voltage.

I asked other users how their non X 1700 CPU behaves under certain idle conditions and my conclusion is: My X CPU does use a fixed offset of +20 C, but on top of that it uses the various dynamic offsets I reported about. That is unless you believe that very specific CPU loads do always lead to a very reproducible increase in temperature by quite exact 10/20 (and maybe 30) C steps.

And now to something completely different:

Tctl vs. Windows power profiles

Some nice +10 C spikes during (mostly) idle times there. Assuming that the reported temps are indeed +20 C higher than real due to a fixed offset, this means that there is another +10 C offset dynamically applied. Since the load did neither vary by amount nor type (as in CPU instructions) I wonder why power profiles have such a big impact on the Tctl behavior!?

It's noteworthy that CPU (Socket) temps don't budge more than 1 C over the whole time-span.

 

[Elixer]

I have an Asrock Taichi with v2.0 bios. I have an rx460 in the PCI-E 1 slot (nearest the cpu) and a NV 1070 in the "middle" PCI-E slot. Running Ubuntu 17.04 beta. I've been trying and failed to do pci-e pass through.

Pretty sure you need the acs patch to make the passthrough work right now, until they can fix the BIOS to change the groupings.

After the memory fixes, it was said that this is also a high priority.

 

[hondaman]

Pretty sure you need the acs patch to make the passthrough work right now, until they can fix the BIOS to change the groupings.

After the memory fixes, it was said that this is also a high priority.

I did the ACS patch and was able to pass my 1070 through to the win10 guest. Got the "error 43" message installing the driver. I couldn't overcome that problem. I guess I'll have to use all AMD/Radeon cards to make it work.

 

[filpo]

Have anybody tried to install a windows server 2012 or 2012 r2 in a am4 motherboard, for instance Asus Prime X-370-PRO?, Do the drivers work?, there are no official drivers for Windows server OS

 

[CatMerc]

https://twitter.com/ryanshrout/status/854152215526813698

Looks like Ryzen's IMC is NOT outsourced. Built in house.

 

[Dresdenboy]

https://twitter.com/ryanshrout/status/854152215526813698

Looks like Ryzen's IMC is NOT outsourced. Built in house.

That's what The Stilt observed.

 

[iBoMbY]

https://twitter.com/ryanshrout/status/854152215526813698

Looks like Ryzen's IMC is NOT outsourced. Built in house.

And why did they outsource 150 AMD R&D developers from that department to Synopsys, and why did they sign a multi-year agreement with them for 14nm, and beyond, technology?

AMD and Synopsys Expand IP Partnership

 

[CatMerc]

That's what The Stilt observed.

Did he? I don't remember him saying that.

Oops.

 

[tamz_msc]

And why did they outsource 150 AMD R&D developers from that department to Synopsys, and why did they sign a multi-year agreement with them for 14nm, and beyond, technology?

AMD and Synopsys Expand IP Partnership

Because being the kind of company AMD is, they need to have a better collaboration between themselves, the foundries to which they are clients, and their EDA tools providers?

I can't seem to figure out what you're getting at by bringing this up here.

 

[guskline]

Looks like a smart move for both companies. AMD gets financial help keeping 150 engineers and Synopsys gains their expertise. Doesn't Samsung have a similar arrangement with AMD?

 

[iBoMbY]

I can't seem to figure out what you're getting at by bringing this up here.

There is no proof whatsoever that AMD is developing their own IMC, only many indications that they are not.

 

[itsmydamnation]

There is no proof whatsoever that AMD is developing their own IMC, only many indications that they are not.

You mean except multi year old linked in resumes that are so far 100% correct.

https://www.linkedin.com/in/amitpapte

RTL Design Engineer working on the Distributed Memory Controller and Directory Cache in AMD's new processors featuring the Zen / K12 cores.

 

[tamz_msc]

There is no proof whatsoever that AMD is developing their own IMC, only many indications that they are not.

No, that deal is about transfer of technology and expertise between AMD and Synopsys. After AMD spun-off its foundry business these kind of deals between it and EDA tools providers is a necessary part of their R&D.

 

[Dresdenboy]

Did he? I don't remember him saying that.

Oops.

I'm pretty certain the DRAM IP isn't supplied by Rambus.
That's because the IPs used in Steamroller and Excavator weren't and Zeppelin has almost identical controller structure (at interface register level) as SR and XV had.

The DRAM controller firmwares are very similar in structure and size as well.
Otherwise I could believe that the IP was supplied by Rambus, but AFAIK Rambus doesn't have any GDDR5 IPs.
Steamroller based parts had DDR3-GDDR5 hybrid controller in them.

While searching, I also found this:

UCLK, FCLK & DFICLK default to half of the effective MEMCLK frequency (i.e. DDR-2400 = 1200MHz).
There is a way to configure the memory controller (UCLK) for 1:1 rate, however that is strictly for debug and therefore completely untested. The end-user has neither the knowledge or the hardware to change it.
AFAIK FCLK & DFICLK are both fixed and cannot be tampered with. However certain related fabrics, which run at the same speed have their own frequency control. The "infinity fabric" (GMI) runs at 4x FCLK frequency.

There are many more fabrics in Zeppelin than just the data fabric.
I'd assume the inter-CCX fabric frequency is 4x DFICLK (i.e. 5333MHz @ 2666MHz DRAM), however I don't know it as a fact.

 

[CatMerc]

While searching, I also found this:

Thanks!

There is a way to configure the memory controller (UCLK) for 1:1 rate, however that is strictly for debug and therefore completely untested. The end-user has neither the knowledge or the hardware to change it.

That's very interesting! Wonder if this was intended for retail and had to be adjusted down, or if it really is strictly for debug.

 

[JimmiG]

Some comparisons of Core Parking enabled vs disabled in 3DMark Timespy.

Core parking disabled:

Core parking enabled:

Definitely getting higher and more consistent XFR frequencies with Core Parking enabled. Interestingly, the CPU temperature also reflects this. You can easily see when it's pumping more voltage into the CPU to sustain 4+ GHz, vs the flat line with Core Parking disabled.

 

[mattiasnyc]

I've got a technical question I'd love for you to help me with...

How does the x370 allocate PCIe bandwidth technically speaking? Is it dependent on the mobo?

I'm looking at the Biostar GT7 (manual) which I'm close to buying, and I'm seeing this:

PEX16_1/16_2: PCI-Express Gen3 x16 Slot
(APU / NPU @x8 + NA speed ; Ryzen @x16 + NA or @x8 + @x8 speed)
• PCI-Express 3.0 compliant.
• Theoretical maximum bandwidth using two slots simultaneously is 16GB/s for each slot,
a total of 32GB/s.

PEX16_SB_1: PCI-Express Gen2 x16 Slot (x4 speed)
• PCI-Express 2.0 compliant.
• Theoretical maximum bandwidth using two slots simultaneously is 2GB/s for each slot, a
total of 4GB/s.

PEX1_1/1_2/1_3: PCI-Express Gen2 x1 Slot
• PCI-Express 2.0 compliant.
• Data transfer bandwidth up to 500MB/s per direction; 1GB/s in total.

Here's what the Asus Prime-370 Pro says:

AMD X370 chipset
1 x PCIe 2.0 x16 (max at x4 mode) *3

AMD X370 chipset
3 x PCIe 2.0 x1

But then the Asus manual notes "***3.PCIeX16_3 slot shares bandwidth with PCIeX1_1 and PCIeX1_3."

In the case of the Asus it doesn't actually say what happens to the PCIex16 slot when I populate either of the other two slots, just that bandwidth is shared. I find that odd because PCIeX1_2 isn't mentioned as being shared. I understand that there is only x4 between the x370 and the Ryzen CPU, but I saw another board where it was specifically stated that if I used the x16 on the x370, AND one of the x1 slots, then the x16 would operate at only x1 speed (if none of the x1 were populated it would have run at x4). But as you can see here Asus just says it's shared bandwidth and Biostar says nothing about it.

So, is there any way I can figure this out or do I just have to ask the seller or manufacturer about it? I just don't want to get an x16 card which I'm ok with running at x4 in a shared configuration only to have it run at x1 only as soon as a card is in one of the 'wrong' x1 slots.

I just have a tough time figuring out these limitations.

 

[Elixer]

With 1 card, you get PCIe gen 3 x16.
With 2 cards, you get PCIe gen 3 x8 (which is the same as PCIe gen 2 x16).
The chipset is PCIe gen 2 x8.
Yeah, different mobos can do things slightly differently depending on what they are doing with the other PCIe lanes.
This explains it quite well.

 

[mattiasnyc]

I know what the deal is with the Ryzen CPU's PCIe lanes, I'm just trying to figure out the x370 usage on different motherboards. I've seen that diagram and I've seen others with the same information and I guess they really just show the 'maximum' available. So it doesn't really help me figuring out those two motherboards for example.

 

[Chl Pixo]

I know what the deal is with the Ryzen CPU's PCIe lanes, I'm just trying to figure out the x370 usage on different motherboards. I've seen that diagram and I've seen others with the same information and I guess they really just show the 'maximum' available. So it doesn't really help me figuring out those two motherboards for example.

I can give you the info for Asus prime X370-pro how the 8 pcie 2.0 lines are distributed:
x1 - intel NIC
x2 - ASMedia USB 3.1 gen2
x1 - PCIE1_1 (2. slot) if used PCIE16_3 will drop to x2
x1 - PCIE1_2 (3. slot)
x1 - PCIE1_3 (5. slot) if used PCIE16_3 will drop to x2
x4/x2 - PCIE16_3 (6. slot)

There is no PCIE spec for x3 so if you use 2. or 5. slot the last slot will have to drop to x2
If they didnt add the ASMedia USB 3.1 they could make the x4 dedicated.
You could look for such board if you need one.

 

[mattiasnyc]

Thank! (to both of you)

Wish I could find the same clear language for the Biostar (though I think it should read "if used PCIE16_3 will drop to x2", correct?). Is that info in the manual?

Interesting trade-offs between the motherboards. If the Biostar offers x4 at all times it might be an interesting option for me.

If anyone is curious; I might do both pro-audio and pro-video work, and it would require an x4 video card believe it or not. I also have (at least) one PCIe 2.0 x1 audio DSP card plus an additional x1 adapter card, so while I might not use both at the same time I wouldn't want one to throttle the other.

 

[Chl Pixo]

Thank! (to both of you)

Wish I could find the same clear language for the Biostar (though I think it should read "if used PCIE16_3 will drop to x2", correct?). Is that info in the manual?

Interesting trade-offs between the motherboards. If the Biostar offers x4 at all times it might be an interesting option for me.

If anyone is curious; I might do both pro-audio and pro-video work, and it would require an x4 video card believe it or not. I also have (at least) one PCIe 2.0 x1 audio DSP card plus an additional x1 adapter card, so while I might not use both at the same time I wouldn't want one to throttle the other.

The Biostar GT7 does only add LAN and everything else is what CPU and chipset provide.
Its highly possible that the x4 is dedicated. You could try to find someone with the board to check.
Most other boards do mention that the x4 is only available with restrictions.
If the USB3 headers had better placement it would be the best board for my needs, still its better match than prime x370-pro i have now.
How good is Biostar quality and support?
Do they supporting Linux, IOMMU and other more workstation oriented functions?

 

[.vodka]

I've searched the thread and looks like this hasn't been posted yet, but it seems we'll have Agner's analysis soon. In the meantime, he says:

RYZEN thoughts?
Author: Agner Date: 2017-04-12 00:52
The single-thread instructions per clock rate of Ryzen is higher than for any Intel processor, except for 256-bit vector code. I am testing the Ryzen right now and the test results are coming soon. Please be patient.

Interesting...

 

[keymaster151]

Does anyone know if you disable cores or SMT manually from BIOS, does this affect the output of the CPUID [EAX=1] instruction? Specifically EBX[bits 23:16] (Number of threads in the processor.) Or is the value static, no matter the changes you make in BIOS?

 

[Dresdenboy]

I've searched the thread and looks like this hasn't been posted yet, but it seems we'll have Agner's analysis soon.

More goodies:

Source:
"Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors"
http://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf