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Ryzen: Strictly technical

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Despoiler said:
From what I have read motherboard auto settings are not working correctly in this respect.
Click to expand...
Well, good news. Of sorts.

Setting VTT_DDR didn't have any effect BUT raising the DDR startup voltage from 1.37 to 1.43 (!) did. It now reboots 3 times and starts up in 3200C14. I'm assuming each F9 reboot it trains with slightly looser subtimings every time?

However, the good news we can take away from this is it's clearly not a Data Fabric speed thing; it seems once it's passes the initial memory POST it's fine.

SOC voltage is same as always, 1.0v
 
First!

And... holy [expletive deleted]!!

AIDA_Cachmem_03272017.png
 
french toast said:
How does than compare to the previous with your ram?
Click to expand...

Memory results didn't change at all.

My former results (at 3.8GHz with DDR4-2133 speeds).

Aiada64_CacheMem_3.8GHz.png


I am rerunning 3Ghz and stock with DDR4-2133 and DDR4-2667 speeds.

Despite 2933 now being doable, it's unstable, so I'm not going to mess with it outside of the memory section of the review (which is slowly coming along - I now have time to devote to it fully).

--

I'd also like to say that this seems to support my results that suggest burst/best inter-CCX latency is actually only 20ns, maybe even slightly less. It's just some coordination or microcode issue - the data fabric is insanely good.
 
looncraz said:
Memory results didn't change at all.

My former results (at 3.8GHz with DDR4-2133 speeds).

Aiada64_CacheMem_3.8GHz.png


I am rerunning 3Ghz and stock with DDR4-2133 and DDR4-2667 speeds.

Despite 2933 now being doable, it's unstable, so I'm not going to mess with it outside of the memory section of the review (which is slowly coming along - I now have time to devote to it fully).

--

I'd also like to say that this seems to support my results that suggest burst/best inter-CCX latency is actually only 20ns, maybe even slightly less. It's just some coordination or microcode issue - the data fabric is insanely good.
Click to expand...
Wow, check out the the L2 and L3 latency, no problem there.
 
looncraz said:
I'd also like to say that this seems to support my results that suggest burst/best inter-CCX latency is actually only 20ns, maybe even slightly less. It's just some coordination or microcode issue - the data fabric is insanely good.
Click to expand...
Wait, what results, did i miss anything? Anyways, "best" inter-CCX latency may as well be intra-CCX, considering that 2*10.8ns = 21.6ns, in line with your results.
french toast said:
Wow, check out the the L2 and L3 latency, no problem there.
Click to expand...
Well, didn't we know that anyway? AMD did mention something like 12 cycle latency for l2 and ~40 (i believe) for l3.
 
lolfail9001 said:
Wait, what results, did i miss anything? Anyways, "best" inter-CCX latency may as well be intra-CCX, considering that 2*10.8ns = 21.6ns, in line with your results.
Click to expand...

I haven't released any specific results... until now, I guess:

Ryzen_Core_Latency_AllCores_a3.jpg


You can see that the average gap between intra-CCX and inter-CCX latency is about 20ns.

There are 192 bits of data sent between cores for the entire process and I am deploying lock-free atomics for synchronization. Swarm mode (the only currently working mode) has the downside of high volatility in the results - this is a simple averaging of three runs.

EDIT:

From those runs, average inter-CCX latency was 25.5ns, peak was 19.2ns.
 
Last edited:
looncraz said:
I haven't released any specific results... until now, I guess:

Ryzen_Core_Latency_AllCores_a3.jpg


You can see that the average gap between intra-CCX and inter-CCX latency is about 20ns.

There are 192 bits of data sent between cores for the entire process and I am deploying lock-free atomics for synchronization. Swarm mode (the only currently working mode) has the downside of high volatility in the results - this is a simple averaging of three runs.

EDIT:

From those runs, average inter-CCX latency was 25.5ns, peak was 19.2ns.
Click to expand...

Why does the last core of one CCX take so much longer to talk to the 2nd last core of the opposite CCX? Is that repeatable?
 
looncraz said:
I haven't released any specific results... until now, I guess:

Ryzen_Core_Latency_AllCores_a3.jpg


You can see that the average gap between intra-CCX and inter-CCX latency is about 20ns.

There are 192 bits of data sent between cores for the entire process and I am deploying lock-free atomics for synchronization. Swarm mode (the only currently working mode) has the downside of high volatility in the results - this is a simple averaging of three runs.

EDIT:

From those runs, average inter-CCX latency was 25.5ns, peak was 19.2ns.
Click to expand...


Is that at 3GHz with DRAM at 2133?
 
Saw some impressive scores on motherboards using external clock generators. RAM stable up to 3400 and results impressive. I will post scores when im home again doing it on mobile is a pain
 
Latest AGESA release candidate appears to unlock BCLK, even on B350 motherboards. YMMV on limitations of BCLK overclocking though, I think the external clockgens on certain boards are still there to avoid some of the side effects of high BCLK and/or give more granularity/stability.

Should be fine to go up a few MHz on BCLK even without, though.
 
looncraz said:
I haven't released any specific results... until now, I guess:

Ryzen_Core_Latency_AllCores_a3.jpg


You can see that the average gap between intra-CCX and inter-CCX latency is about 20ns.

There are 192 bits of data sent between cores for the entire process and I am deploying lock-free atomics for synchronization. Swarm mode (the only currently working mode) has the downside of high volatility in the results - this is a simple averaging of three runs.

EDIT:

From those runs, average inter-CCX latency was 25.5ns, peak was 19.2ns.
Click to expand...

So if the DF Latency is about 25ns max., that still doesn't explain the memory latency. Even if we add the L3 Latency + 2x DF Latency + Memory Latency we still would have lower values than the actual readings.
 
Can't confirm but

Zen HEDT CPU's are called Threadripper!
Each CPU will include 64 PCI-E Lanes!
It includes 4 CCX's.
Lower SKU(Probably 12/24) 140W TDP, Higher SKU (Probably 16/32) 180W TDP.
Socket will be an SP3 LGA
Platform's name will probably be X399
Chips will be B2 revisions.
32MB L3 Cache
ES's are 3,3 or 3,4 Ghz base and 3,7 Ghz Boost
It is aimed for Retail SKU to have 3,6 Base/4 Ghz Boost
ES's that are in the wild have 2500 CB R15.
Infinity Fabric can have a bandwidth up to 100GB/S
Announcement; COMPUTEX at Taiwan, sales will start after 2-3 weeks following COMPUTEX.

Wow
 
OrangeKhrush said:
Can't confirm but

Zen HEDT CPU's are called Threadripper!
Each CPU will include 64 PCI-E Lanes!
It includes 4 CCX's.
Lower SKU(Probably 12/24) 140W TDP, Higher SKU (Probably 16/32) 180W TDP.
Socket will be an SP3 LGA
Platform's name will probably be X399
Chips will be B2 revisions.
32MB L3 Cache
ES's are 3,3 or 3,4 Ghz base and 3,7 Ghz Boost
It is aimed for Retail SKU to have 3,6 Base/4 Ghz Boost
ES's that are in the wild have 2500 CB R15.
Infinity Fabric can have a bandwidth up to 100GB/S
Announcement; COMPUTEX at Taiwan, sales will start after 2-3 weeks following COMPUTEX.

Wow
Click to expand...


Will someone buy my R7 1700X?

What does your Crystal Ball says re B2 revisions. It seems pretty clairvoyant thus far.
 
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