Take that result with a grain of salt for now. I have had a look at the comment section and the reviewer said that He forgot to disable the "double buffering" on the 7700k part. Now that it is disabled, the result is here:
The PCH (platform controller hub - a.k.a. the "chipset") only uses some 6~8W of power total.I have an ... interesting request.
Can you disable as much I/O as possible on the chipset (while using the I/O from the CPU) and try to quantify what power savings it might generate?
With an undervolted CPU, might as well try to push further.
Would also give us a better idea on the power savings X300 might get us.
The PCH (platform controller hub - a.k.a. the "chipset") only uses some 6~8W of power total.
Two cores share one FPU. For the performance it's better to assume they work like SMT cores, than to ignore the fact.I seen other people posting this as well. Coreinfo says that FX 8350 is hyperthreaded.
It must be wrong lol
Logical to Physical Processor Map:
**------ Physical Processor 0 (Hyperthreaded)
--**---- Physical Processor 1 (Hyperthreaded)
----**-- Physical Processor 2 (Hyperthreaded)
------** Physical Processor 3 (Hyperthreaded)
******** Group 0
So basically what you are saying is that overclocks cause it to fall into Gen 2 or Gen 1 automatically?Verify in what respect?
Sure, you can hit those BCLKs if you set the PCIe to run in Gen. 1 mode.
If everything is on one CCX, then the last level cache becomes that CCX's L3 and not the DRAM, unlike with 2 CCX enabled.wow that Ryzen tested as quad core at 4 ghz against a 7700k at 4 ghz is quite good. In fact the inter CCX bandwidth problem is automatically solved by having a single CCX with all 4/8T. I think if AMD can use a single CCX for R5 1500x with clocks of 3.9-4.0 Ghz for 1-2 cores and 3.7 Ghz for all core turbo then it would be a very good gaming chip too especially if AMD can price it at USD 179 (instead of USD 199). It will basically be very close to core i5 7600k but at a significantly lower price. In fact Intel's non k Skylake chips would have a tough time against it.
No, you need to manually place the PCIe from Gen.3 (default) to Gen.2.So basically what you are saying is that overclocks cause it to fall into Gen 2 or Gen 1 automatically?
Also, why is the Uncore different? I thought the Uncore was at the same speed as the Core itself? From what I understand, cache speed operates at the highest core speed. So in this case, the CPU was idling and the highest cache was at 1.8 GHz, rather than say, the maximum clock speed?
If everything is on one CCX, then the last level cache becomes that CCX's L3 and not the DRAM, unlike with 2 CCX enabled.
There is no "uncore" in Ryzen.Thanks that makes a lot more sense.
Hmm ... that makes me wonder about the data fabric speed.
- Data fabric at 50% of RAM speed
- Uncore is tied to core speed
- Base clock (or Refclock) is tied to PCIe , and can only go to about 105 MHz at 3.0, but then has to go to 2.0
From reading Elmor's guide it happens automatically on CH6 or have I got wrong end of stick?No, you need to manually place the PCIe from Gen.3 (default) to Gen.2.
Has your experience been different on CH6The above values are based on the Auto-rules and are a good indication of the margins. PCI Express bandwidth values are at default 100MHz REFCLK and increases linearly when increased. From internal testing most PCI Express devices including graphics cards and storage controllers handle increased REFCLK very well. At the moment there’s no list with proven devices.
The software / firmware can only alter things that are supported by the hardware itself.Stilt, since we cant raise or alter certain clock rates directly, assuming firmware could be presented to lie to the UCLK or fabric, would that be an adequate solution to their limited variability? Either by bifurcating information to the system agent reading the MEMCLK, or by creating a secondary path which is only read by the fabric and UCLK? Fixing the issue of control by Breaking traditional standards so to speak?
For example: lets say you had 3200mhz ram. This would normally limit UCLK and fabric rates to 1600mhz. With alterations, the firmware was then made to lie to the fabric, but the normal system still treated the memory as the correct 3200mhz rate. The Fabric/UCLK are meanwhile sent incorrect information modified by a multiplier(say in this instance 2x or 6400mhz False MEMCLK) resulting in the UCLK and fabric reaching parity with the True MEMCLK at a 1:1 ratio.
If the user cannot access these Rates directly on the motherboard this seems like an amenable solution to the problem. Testing would still need to be concluded to determine maximums, safe 24/7 rates and voltages. Has something like this ever been done before in the past? At the moment this seems like the only possible solution to the end user if it works.
Yes, "OC-Mode" is only activated by increasing the P0 PState effective ratio. By using BCLK you can somewhat extend the frequencies, while maintaining the normal CPB & XFR operation.Hey Stilt, fellow Finn here. Thanks for the awesome post. I learned much more in these 15 pages than from the other tech sites combined.
I was wondering about the feasibility of a mild BCLK overclock with the following goals in mind:
From my understanding of your discussion on OC mode, it isn't triggered by BCLK or Vcore tweaks--only multiplier. If that is correct, would we be able to extend XFR's max clock? I would assume it isn't hard capped at 4.1 on the 1800x for example, and is rather a byproduct of (BCLK)*(Multipliers)+(XFR offset).
- Not entering OC mode, thus not forcing the CPU to run in P0 state
- Slightly boosting memory and interconnect speeds
- Increasing the max range of XFR, boosting single thread performance without sacrificing the ability to clock down when idle.
Furthermore, if OC mode isn't triggered by BCLK adjustments and as you said earlier, 107 is the highest you can go while maintaining PCIe gen 3 stability, would it make sense to just use a BCLK of 102 for example (I think the default is 100 right?) to get a 3672mhz base / 4080mhz boost clock where one core can boost up to 4180mhz under XFR? This is of course assuming you could get the system stable at those clocks.
And would using Zen master profiles to avoid unwanted high idle power consumption be a good workaround to have OC when you need it and good power consumption when you arent running specific stressful apps?Yes, "OC-Mode" is only activated by increasing the P0 PState effective ratio. By using BCLK you can somewhat extend the frequencies, while maintaining the normal CPB & XFR operation.
However as said before, I personally do not recommend increasing the BCLK even by a single MHz. It's not the way these chips were designed to operate and increasing the BCLK even slightly can cause issues.
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