Discussion Ryzen 9000X3D series review thread

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AMD, for heaven's sake just give us 9900X3D with dual V-cache CCDs.

Look, this way you can sell more busted dies!

I mean, PUHLEEEZZZEEEEEEEE!!!!! (in Jim Carrey's voice).

I bet I could charm Lisa into releasing this CPU if I could just appear in front of her.
 

fastandfurious6

Senior member
Jun 1, 2024
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yeah negligible benefit

you know 95% of performance reviews and questions and dives etc would be easily replaced by a solid contextual perf profiler

very good market opening tbh, easy millions. proper AI done right enables this kind of software now

still needs years I guess. would be chips&cheese level analysis done by instrumental software and controlled agentic AI
 

mikeymikec

Lifer
May 19, 2011
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LightningZ71

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Anything on CPU package to reduce mainboard complexity should be a win for consumers. I still believe the first 8-16 GB of RAM should be on the CPU package. NUMA should be mainstream in 2025.
CXL has been in existence for over 6 years now, and currently supports a PCIe 6.0 hardware layer. Having 16GB on package with an x16 6.0 link to a CXL memory hub can solve a ton of memory issues. Just clearing out room around the socket for airflow and power delivery circuits alone would be a boon. Yes, you do sacrifice a bit of ram memory bandwidth for the above 16GB portion, but the exchange may be worth it.
 

DAPUNISHER

Super Moderator CPU Forum Mod and Elite Member
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I'm curious to know how linked ASUS and ASRock are on an operations level. I would have thought that since ASUS apparently aren't having problems on this front then whatever skills/knowledge necessary could be communicated across to their sister/daughter company. It would surprise me if their methods are so different.
According to Wiki; While Asus still owns a almost 20% stake in Pegatron, they have not had any direct operational influence over ASRock since 2008.
 

StefanR5R

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Dec 10, 2016
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Anything on CPU package to reduce mainboard complexity should be a win for consumers.
While reduced complexity can be beneficial, it also may be detrimental to customers, most notably if it reduces flexibility ( = the possibility to adapt to user requirements, and do so at moderate cost).
I still believe the first 8-16 GB of RAM should be on the CPU package. NUMA should be mainstream in 2025.
Tiered RAM would increase hardware complexity though. And NUMA in general and tiered RAM in particular increase software complexity.
[Edit: Perhaps I read too much into the proposal of combined on- and off-package RAM. Might not be a tiered setup, just a nonuniform setup.]
CXL has been in existence for over 6 years now, and currently supports a PCIe 6.0 hardware layer. Having 16GB on package with an x16 6.0 link to a CXL memory hub can solve a ton of memory issues. Just clearing out room around the socket for airflow and power delivery circuits alone would be a boon. Yes, you do sacrifice a bit of ram memory bandwidth for the above 16GB portion, but the exchange may be worth it.
CXL attached RAM, while tending to offer less bandwidth than RAM on an IMC, does at least increase the aggregate RAM bandwidth of the overall system (if it is there in addition to IMC attached RAM). But what matters most in the client segment is that CXL attached RAM has greater access latency than RAM on an IMC.
Meanwhile, moving a portion of IMC attached classic DRAM from mainboard to package does not decrease its access latency, or does it?
 
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Meanwhile, moving a portion of IMC attached classic DRAM from mainboard to package does not decrease its access latency, or does it?
What if they used latency optimized DDR5? And the latency benefit could be segmented like so:

Ryzen 3 5600C28 8GB
Ryzen 5 6000C28 12GB
Ryzen 9 6400C28 16GB

A bit more engineering effort and they could get each of those CAS latencies down to C26. These would be factory optimized with the best possible subtimings. No need to let the user mess with these. Memory trains quickly as a result.
 

MadRat

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The immediate benefit of on package RAM would be control of tighter timing and power regulation for the closest RAM to the cores. It would be tightly synchronized with the infinity fabric clock. RAM outside this optimized set obviously pays a higher timing penalty, but due to distance from the core higher latency is inevitable.
 

fastandfurious6

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Jun 1, 2024
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32/64gb ram is all one needs for system, except LLMs

set aside a couple of extra dimm slots just in case for LLM use cases but not mandatory

what is the sacrifice for on-die ram?

arguably Halo model is better than on-die
 

MadRat

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Seems like CXL support is literally mapping memory point to point between devices. Seems by the time Zen 6 comes out it may make sense to have extra DIMMs on videocards, where it reduces the average consumer's need for more than 2-4 mainboard attached DIMMs. The videocard would benefit yet anytime the system hits it the response is far quicker than an SSD. The writing was on the wall when SSDs starting being attached to videocards. Mainboard complexity should drop over time. I could only guess mainboards will also continue to shrink as a result.
 

StefanR5R

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Graphics cards which double as an M.2 riser card have remained obscure one-off projects without any market impact — as far as I am aware.

Regarding memory add-in boards: There were some available for various microcomputer platforms in the 1980ies, early 1990ies. I don't see this concept to experience a renaissance in client computers. In some large-memory server segments perhaps (I am not as sure about more general adoption of CXL memory in servers as the usual CXL news coverage is), with increasing PCIe speeds making them more viable compared to what is possible currently.

After all, what is a memory-only CXL device? It is almost exactly the same as yet another Central Processing Unit + associated DIMMs, except that this CPU doesn't have regular CPU cores; but it has got all the un-core shebang. AMD could cater to this market with 0-core EPYC SKUs, put into BGA package and soldered onto respective daughter boards... ;-)

As I see CXL memory expanders unlikely to become popular in client computing, I consider it even less likely for client GPU vendors to integrate a CXL memory expander onto a graphics card.
 
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LightningZ71

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I see it as a way to elevate computer performance another notch. If we're looking to move some RAM closer to the CPU in the interest of increasing available bandwidth, we will limit capacity. Capacity is still important in some circles, so that's a no-go.

Looking at what we have now, they can integrate LPDDR5x at high bandwidths. They can deal with the added latency by adding L3 cache, but you need capacity. You can add that with an x16 6.0 channel to a CXL chip with a few RAM slots connected to it. The only difference is that the OS needs to be NUMA aware, but both Windows and Linux already are.
 
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StefanR5R

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the OS needs to be NUMA aware, but both Windows and Linux already are.
"NUMA awareness" can mean anything and nothing.

Performance degradation due to NUMA can be prevented by
– manual performance tuning by the admin (not happening in usual client scenarios),
– automatic performance tuning by the application (likewise not happening),
– automatic performance tuning by the OS.

For the latter, and a memory setup like you describe (1 NUMA node with CPUs and memory + ≥1 NUMA node without CPUs but with memory), the operating system kernel needs to perform transparent movement of virtual memory back and forth between near and far physical memory, based on how the virtual memory is being accessed. And of course applying heuristics, which can backfire. Copying memory has its cost obviously, so there needs to be a balance between trying to keep heavily accessed memory near on the one hand, yet not pulling pages from far to near memory (and vice versa) too eagerly on the other hand.

Linux does this optionally. I am not up to speed whether or not this is enabled by default in popular Linux distributions. As for Windows, I don't know if it can do that (or rather, which Windows editions can do that), and if yes, if it is enabled by default.
 
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Dave3000

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I have a 9800X3D and I noticed in OCCT in the normal CPU and the Linepack 2021 stability tests that my CPU will stay at slightly over 4.7GHz then after 30 seconds or so drop a little below its 4.7GHz base frequency as it gets closer to its 95C Tjmax temperature and it gets closer to 4.6GHz than 4.7GHz about a minute of staying at the 95C Tjmax in these two tests. The Linepack 2019 stability test, my 9800X3D stays between 5 to 5.2 GHz even at the 95C Tjmax temperature and the same with Cinebench R20. I use a Noctura U12A CPU cooler to cool my 9800X3D. Should my CPU guarantee it's 4.7GHz base frequency, no matter what, since it's advertised with a 4.7GHz base frequency? I thought base clocks were guaranteed minimum clocks by the manufacturer of the CPU no matter what. During gaming, it is usually running at 5.2-5.25GHz.
 
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Dave3000

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That's why I said "I thought". Back in the time CPUs did not have a turbo boost feature and only a base clock, would they throttle below their advertised frequency if they started to overheat or reach a specific temperature or would they just continue to stay at their advertised frequency and eventually shutdown the system or kill the CPU due to overheating or would they throttle as well? Also my 7800X3D in my secondary system runs much cooler, much quieter, and consume much less wattage during these two tests in OCCT, even with a CoolerMaster Hyper 212 Black, and stays slightly above its base frequency, however, my 7800X3D consume less wattage and runs at a lower frequency than my 9800X3D.