Rumour: Bulldozer 50% Faster than Core i7 and Phenom II.

[Nemesis 1]

It was obvious where you were leading the dialogue, which is why I added this:



Of course intel had no control over retail PIB, and why AMD had great channel business. intel's goal was to block AMD from large OEM business' like Dell. Brand recognition was obviously intel's biggest concern, because if nobody here's of them, they are no threat to business. If consumers knew there was a better alternative, you can bet demand would increase, and funding made available for Fab expansion.

last OT from me

Enough . Stay on track . everthing is here in black and white . Those who count can read very well.

 

[Ben90]

Basically every post has been off track since the OP. Acceptable on track responses include:

Nice rumor


I vote we continue going off in different directions within this thread. Its nice coming into this thread every day and reading about some random thing instead of having it be on page 20. You can only tell people that their processor isn't overheating so many times before it becomes old.

 

[Elixer]

Speaking about facts, I thought you were going on vacation?
Now, if you are on vacation, you can pretty much bet that there is going to be no launch without one of the bigwigs (that is you JF!) around.. so...
And yeah, I know, JF is the server guy, not desktop.

How many times does he have to say that he's in the server dept? Server has always been Q3, anyway. He's probably getting his vacation out of the way now b/c he knows he'll be very busy later this year.

Erm, looks like that part went over your head.
At least you deducted why he is taking a vacation now, and not later.

 

[Abwx]

Rumours of BD delay may be true since AMD is in absolute need
of supplying mobile variants of Llano to overcome the shortage
of Bobcat CPUs, thus using all possible 32nm capacities for Llano.

http://www.engadget.com/2011/05/28/amd-ships-five-million-fusion-chips-says-its-sold-out/

 

[nonameo]

Rumours of BD delay may be true since AMD is in absolute need
of supplying mobile variants of Llano to overcome the shortage
of Bobcat CPUs, thus using all possible 32nm capacities for Llano.

http://www.engadget.com/2011/05/28/amd-ships-five-million-fusion-chips-says-its-sold-out/

can't they just buy more capacity from TSMC for that? bobcat's on 40nm anyway, right? I don't really think llano is in the same tier as bobcat.

 

[Tuna-Fish]

can't they just buy more capacity from TSMC for that? bobcat's on 40nm anyway, right? I don't really think llano is in the same tier as bobcat.

TSMC 40nm has been running at capacity pretty much from launch. Buying more means either less Radeons, or competing for the capacity with nVidia.

 

[JFAMD]

sorry jfamd but i don't understand one thing:

the turbo is fixed to the max frequency or is variable at intermediate multiplier settings?

for example:

defaulf frequency: 3ghz
all core boost: 3.5ghz

the all core boost can auto-adjust also at 3.1-3.2-.3.3-3.4ghz for match the tdp or is fixed to 3.5?

It is variable but the max is the max. So all core boost would default (in your case) to 3.5GHz, but it you were near the top of your power budget it might drop to 3.4GHz instead of dropping back to base.

Erm, looks like that part went over your head.
At least you deducted why he is taking a vacation now, and not later.

I use my frequent flyer miles to book my vacations (I fly ~150K+ miles per year, so they build up quickly). My vacation starts next week and was booked last july. Thanks for obsessing about me though.

 

[Cerb]

I didn't find one of the nice IPC over time diagrams I have somewhere on my HDD.

The best I could find was this one, off-hand, but it's over the course of whole tests, just for Conroe (BZip2 was quite a surprise, actually):
http://www.ece.lsu.edu/lpeng/papers/isast08.pdf

Do you have the module concept in mind here? Otherwise delivering more than X decoded ops per cycle while execution only processes them at a maximum rate of X would be no bottleneck.

"That leaving execution starved, with code that offers high ILP, seems like a silly thing to do, compared to matching the capability end to end, to prevent inefficient execution of efficient code."

Again, I must refer to the Captain (motto: never pass up a chance to reference that, the hard boiled egg scenes, or plastic Jesus). How is that not basically the same thing? If most code only runs at <=1 IPC, but you can either find some, or have reasonable good simulations of workloads you want to be good for, able to manage ~1.5 in some oft-run loops, if not limited by the front end, would you make a front end as close to 1 instruction per cycle as possible--the common case--or try to make sure it can manage >=1.5 all day long?

Now, if >=1.5 basically means around 2, and you add a processor, you add another 2 for that processor (assume RISC, so it's not a binary-dependent, nor that there is the duplicated complex decoder). With a shared setup, 3 would be enough to take care of peaks, and the total width would be less than that of two single-threaded processors. It would only be the very rare care cases where that 1.5 could be exceeded by both at the same time, for some length of time, that it would be slower, but this would be both highly uncommon (as defined by being difficult to come up with programs that can do it, processing something akin to real data), and with higher ILP code tending to be less sensitive to CPI, making up for it elsewhere shouldn't be hard (such as those increasing the actual IPC of more common cases...OK, that is hard, but it's also far more important, as a 2&#37; improvement across the board is better than worrying about a 2% hit in 1/10,000 of performance-oriented programs).

 

[drizek]

It is variable but the max is the max. So all core boost would default (in your case) to 3.5GHz, but it you were near the top of your power budget it might drop to 3.4GHz instead of dropping back to base.



I use my frequent flyer miles to book my vacations (I fly ~150K+ miles per year, so they build up quickly). My vacation starts next week and was booked last july. Thanks for obsessing about me though.

So at a given frequency and voltage, you can have substantial differences in power draw just based on the kind of workload? So two tasks that are "maxing" the cpu, but in different ways, will use substantially different amounts of energy?

 

[Idontcare]

So at a given frequency and voltage, you can have substantial differences in power draw just based on the kind of workload? So two tasks that are "maxing" the cpu, but in different ways, will use substantially different amounts of energy?

This is true but I can't tell if you are asking the question facetiously or if you earnestly don't know and are curious if it is true and why.

Different instructions require differing logic structures for their computation, those differing logic structures are laid out with differing amounts (and sized) transistors. No two instructions consume the same amount of electricity.

Different programs with different mixes of instructions will consume differing amounts of max power.

This is why, for example, both Prime95 small FFT's and large FFT's will "max" the CPU but the small FFT routines will result in more power consumption which results in higher operating temps.

 

[drizek]

I kind of assumed that that was the case, but I hadn't really thought about it before. I never thought that it would make a big enough difference to warrant a 500MHz underclock, although that might only apply to a 16-core server chip.

So it just different transistor types in the core or is it more about cache?

 

[wahdangun]

It is variable but the max is the max. So all core boost would default (in your case) to 3.5GHz, but it you were near the top of your power budget it might drop to 3.4GHz instead of dropping back to base.



I use my frequent flyer miles to book my vacations (I fly ~150K+ miles per year, so they build up quickly). My vacation starts next week and was booked last july. Thanks for obsessing about me though.

so is that mean, if I lowering the voltage I can expect higher turbo boost ?

 

[Tuna-Fish]

I kind of assumed that that was the case, but I hadn't really thought about it before. I never thought that it would make a big enough difference to warrant a 500MHz underclock, although that might only apply to a 16-core server chip.

So it just different transistor types in the core or is it more about cache?

I'd say it's more about the amount of transistors that you need to touch per clock. For example, if your code is a balanced mix that frequently uses all the SSE/Integer units, you can expect most of the core to do work every clock. If you do a simple integer loop, the entire floating point part can be shut off to conserve power. Don't divide anything this clock? Don't need to use the barrel shifter? All this frees power from the absolute peak.

so is that mean, if I lowering the voltage I can expect higher turbo boost ?

Well, lowering the voltage drops the frequency headroom. If you're not very careful, you can expect crashes when the processor tries to turbo

 

[drizek]

Bad news from Computex:

Just above Llano we will have the long awaited Bulldozer CPU. AMD originally wanted to launch Bulldozer at Computex but performance issues with its B0 and B1 stepping chips pushed back the launch. Now we're looking at a late July launch with B2 silicon, but performance today is a big unknown. Apparently the performance of B1 stepping silicon doesn't look too good.

Bulldozer will be mechanically compatible with Socket-AM3 motherboards but AMD will only officially support the CPU on AM3+ motherboards. To differentiate AM3+ from AM3 motherboards AMD is releasing a new chipset: the 9-series. Functionally the 9-series chipset is no different from the 8-series that it replaces; it'll simply be used on AM3+ boards exclusively.

So Bulldozer is:

1. Delayed
2. Slow
3. Doesn't improve SATA performance.

Let's hope it's cheap...

 

[skipsneeky2]

/\ if the above post is to be true, that doesn't look good at all.

Well besides it support current am3 sockets thats good news for the amd fans out there.

Wish intel could take off from this , besides offering 3 different sockets every 2 years.

 

[Nemesis 1]

/\ if the above post is to be true, that doesn't look good at all.

Well besides it support current am3 sockets thats good news for the amd fans out there.

Wish intel could take off from this , besides offering 3 different sockets every 2 years.

Would that be both the white socket and black socket . If so thats news If its black socket old news.

Intel is moving at 3x Amds speed on product development so a new sockets is nothing to bind panties over . Llano on a new socket . When SoC comes to BD it to will likely be a new socket .

 

[Abwx]

Bad news from Computex:

So Bulldozer is:

2. Slow
.

Was Anand briefed by AMD s engineers and explicitly told
that performances not as high as expected was the issue ?..:biggrin:

Or is it wild speculations..?..:whiste:

 

[Nemesis 1]

Calling Anand out at his site is really not smart. I to thought that was alot of information. Anand wanted to see BD out sooner than later. So I believe the information he is giving as it pretty much matches what robert has told us. I will see him tomorrow as he is coming over to help my wife set up the new system he gave her this week on the test bench . I will see if he has anything to add.

 

[Nemesis 1]

Was Anand briefed by AMD s engineers and explicitly told
that performances not as high as expected was the issue ?..:biggrin:

Or is it wild speculations..?..:whiste:

Not every body was expect high performance in single thread performance fact is many were expecting a dog in single thread . AMD should never have jumped over K9 as they been making nothing but dog cpus since k8

 

[Riek]

Not every body was expect high performance in single thread performance fact is many were expecting a dog in single thread . AMD should never have jumped over K9 as they been making nothing but dog cpus since k8

the only ones who were expecting a dog in single thread are those that have a severe lack of knowledge.
Wether or not AMD can deliver is another part of the equation, but there is no single thread performance issue in the design and projections. It is the manufacturing part that is at miss.

AMd never jumped over K9, K9 was never made. current thuban are still based on K8. K10 and others are not the names given by AMD but by some wierd people on the internet.

 

[Nemesis 1]

Give it a rest . SO AMD never used K9 but did a K8 thats a jump over , You been lead like a little lamb. I never seen anything good in amds design . AVX is a joke on BD 128 +128 = 256 vs intels 256 . all the talk and there really isn't anything there, IPC per core will be slower period. As AVX doesn't count yet as none have figured it into SB IPC over generation 1 . SB is at least 20 faster than generation 1 or it wouldn't be Kicking intels highest end cpu around . That has 2 more cores . Ya I know its slower in multi threads but not by much . Yet the losers still use the 15&#37; figure its really amusing . TO top it off ya blame GF that is rich . The fabs moved out of germany and hired all new people . Really .

 

[Terzo]

Bad news from Computex:

Just above Llano we will have the long awaited Bulldozer CPU. AMD originally wanted to launch Bulldozer at Computex but performance issues with its B0 and B1 stepping chips pushed back the launch. Now we're looking at a late July launch with B2 silicon, but performance today is a big unknown. Apparently the performance of B1 stepping silicon doesn't look too good.

Bulldozer will be mechanically compatible with Socket-AM3 motherboards but AMD will only officially support the CPU on AM3+ motherboards. To differentiate AM3+ from AM3 motherboards AMD is releasing a new chipset: the 9-series. Functionally the 9-series chipset is no different from the 8-series that it replaces; it'll simply be used on AM3+ boards exclusively.

So Bulldozer is:

1. Delayed
2. Slow
3. Doesn't improve SATA performance.

Let's hope it's cheap...

Is there more to the bolded part? It sounds like you'd be able to just drop Bulldozer into any old AM3 board, supported or no, and have it work.

 

[Abwx]

I never seen anything good in amds design . AVX is a joke on BD 128 +128 = 256 vs intels 256 ..

You are making fool of yourself..

When only 128 bit datas are issued by the scheduler ,
AMD s FP execution unit can execute two simultaneously ,
while SB will be stuck at one 128 bit data per execution unit,
though it will execute two if AVX is implemented, and this only
when very well opimised code is implemented.

In short, BD will have very high FP single thread performance
even with current SSE code while SB will have to wait for
optimised softwares that will only allow it to be on par with BD.

 

[Cerb]

Hopefully it will be OK when it does come out. On one hand, we'd all like to see it out, and see what it can do, sooner, not later, but OTOH, Llano is the one they really need to get out to end users before college kids go back to school. If BD isn't competitive in a month or two, it won't be impressive right now, either. If Llano misses back to school, I could see upcoming lower-end CPUs from Intel making it too little, too late. Getting back to school done, I could see that inertia working for them right through the new year.

 

[Riek]

Give it a rest . SO AMD never used K9 but did a K8 thats a jump over , You been lead like a little lamb. I never seen anything good in amds design . AVX is a joke on BD 128 +128 = 256 vs intels 256 . all the talk and there really isn't anything there, IPC per core will be slower period. As AVX doesn't count yet as none have figured it into SB IPC over generation 1 . SB is at least 20 faster than generation 1 or it wouldn't be Kicking intels highest end cpu around . That has 2 more cores . Ya I know its slower in multi threads but not by much . Yet the losers still use the 15&#37; figure its really amusing . TO top it off ya blame GF that is rich . The fabs moved out of germany and hired all new people . Really .

There is no jump since their is nothing after K8.. That is called a jump away.

AVX implementation is a joke compared to SB in peak yes. Yet it is an unused, need to be recompiled to work instruction and SB/BD module haver the same sustainable AVX throughput.
FMA implementation in SB is a joke.. same arguments as above: unsused, needs to recompiled. (not even present in SB) value of this instruction is in the same facinity as AVX. AVX increases throughput on SB, FMA does the same for BD.

edit: what i forgot to mention. AVX and FMA support is not what will make both cpu's succeed. Those are mostly irrelvant in performance or design equadion for now.

ipc/core will be lower, compared to what? I'm pretty confident the ipc/core will be higher then athlon, bobcat, atom, p3, p4, p2, pentium.. Or do you mean compared to sandy bridge? Well it is a design that is created to allow higher frequencies, so it is a trade of between the two metrics determining performance.

Also ipc/core is not important. ipc for an application is important. core numbers/thread numbers/ are all irrelevant for this. there is no average ipc for all applications. And cpu's become more and more focussed on certain aspects of performance.