Discussion RDNA 5 / UDNA (CDNA Next) speculation

[Win2012R2]

Why are you changing the discussion to DF?

Because you brought it up! Glad we agree they are not an Nvidia shill, they are a professional outfit that obviously makes Nvidia want them to cover them, which is why they get pretty good access others don't.

However DF does not shape popular opinion, they are the source for people who already have brains and don't believe blindly stuff shills put out.

 

[coercitiv]

Because you brought it up!

You brought up the shilling! I responded by explaining that Nvidia shills can do more damage in the absence of FSR4 updates for RDNA3/2. I then proceed to SARCASTICALLY show the DF video as evidence that AMD already received balanced coverage from the press, making a negative turn that much more unlikely.

large Nvidia shills PR network.

Do you have evidence that Nvidia work accounts for at least 10% of their revenues?

 

[Win2012R2]

You brought up the shilling!

Yes I did, and then you brought up DF and it wasn't sarcastically:

"For example look, at this negative coverage of FS4 INT8 on RX 6700 from Digital Foundry:"

Can't see any sarcasm here, was not really inclined to watch video, maybe next time avoid "sarcasm"?

Do you have evidence that Nvidia work accounts for at least 10% of their revenues?

I can see evidence of shilling for a bunch of them as they rely on "access journalism".

 

[Momoka_]

They are a press outlet with a very strong financial relationship to Nvidia. I did not chose them for this reason though, and I don't view them as shills. They like new tech a lot, and they understand hardware limitations and IQ issues better than the average press outlet or youtuber. I believe their preview Illustrates my point that the press wants to cover this tech in a positive/balanced fashion.

As for the real shills, reddit is already echoing with voices claiming AMD does not support their GPUs. They pop on AMD GPU news threads, the noise is constant, the damage is ramping up. The only question that comes now is whether AMD can counter this by stepping up for their customers. If they don't chose to support FSR4 on RDNA3 then so be it, but at least accelerate feature updates for RDN4.

A few days ago I stumbled on this post from Ancient Gameplays, who is usually very pro-AMD in his coverage:

https://twitter.com/x/status/2021741507422908732

From what I’ve heard, to stay competitive with Nvidia in data center GPUs, AMD has reallocated many Radeon employees to the data center division to support the rapid update cycle of CDNA and ROCm. Nevertheless, this should not serve as a justification for the delayed progress of RDNA4.

 

[coercitiv]

was not really inclined to watch video

that settles it then.

 

[adroc_thurston]

From what I’ve heard, to stay competitive with Nvidia in data center GPUs, AMD has reallocated many Radeon employees to the data center division to support the rapid update cycle of CDNA and ROCm.

Newsflash, Nvidia did the same.

 

[Win2012R2]

that settles it then.

I did not watch it because I took your word for it being negative.

 

[Momoka_]

Newsflash, Nvidia did the same.

Of course, Nvidia has been doing this ever since the Mellanox deal.

 

[Win2012R2]

If "Magnus" is all ready already (physical design, "all wires signed off")as MLID claims then surely AMD's RDNA5 card should also be kind of ready too? Then why fecking wait - launch top model, higher mem prices will be less visible there.

 

[Kepler_L2]

If "Magnus" is all ready already (physical design, "all wires signed off")as MLID claims then surely AMD's RDNA5 card should also be kind of ready too? Then why fecking wait - launch top model, higher mem prices will be less visible there.

Post-Si validation

 

[Win2012R2]

Post-Si validation

How long does that take?

MLID gave impression that Magnus is basically all ready to go as design is finalised.

 

[CakeMonster]

If they decided to delay the console by say ~2 years because everything is borked, what if anything would they be able to improve or iterate on in that time? I realize most of the SoC design is locked down but can they realistically add anything to it?

 

[Tachyonism]

If they decided to delay the console by say ~2 years because everything is borked, what if anything would they be able to improve or iterate on in that time? I realize most of the SoC design is locked down but can they realistically add anything to it?

Any changes after tape-out will be very costly.

 

[Momoka_]

Any changes after tape-out will be very costly.

However, this implies that the console will remain very expensive during its initial launch period. Due to increased capacity and a long-term DRAM production shortage, the cost of GDDR7 is expected to be quite high.

 

[1250]

I don't know if I can write this here
I believe AMD uses a custom HBM for mi455x. The Samsung community treats me like an idiot. I don't intend to convince them; I just want to be reassured. I'll write about their claims separately.

 

[1250]

I believe AMD uses a custom HBM. I just want to be reassured.

Is NDA a problem?
At least it would be nice to know that MID doesn't have a lpddr phy.
Or I'd like to know the package size at least.

1. Development costs exceed $100M, making it inefficient.
2. The base die cannot be made compatible with the core dies of the three memory companies.
3. Insufficient capabilities.

4. Custom HBM starts with HBM4e (Samsung and Hynix have created dedicated custom HBM teams)

If you ask them about the location of the LPDDR PHY, they won't be able to answer.

 

[ETI4711]

I don't know if I can write this here
I believe AMD uses a custom HBM for mi455x.

AFAIU is custom HBM quite common for HBM4.

The Samsung community treats me like an idiot. I don't intend to convince them; I just want to be reassured. I'll write about their claims separately.

Semianalysis shows that AMD had an easter egg in the CES 2026 presentation (17:20). There are 24 LPDDR5X packages ...

https://twitter.com/x/status/2013310524109328580

The Question is, were are the memory controllers for these LPDDR5X packages?

US20250098181A1 "Integrated Memory Controller Circuitry" may be the answer: in the custom base die of the HBM stack.

If that's true were are the LPDDR packages located:

substrate? possible not, there is too much distance ...

or PCB?

 

[1250]

제가 알기로는 HBM4에서 커스텀 HBM은 꽤 흔한 것 같습니다.

부분 분석 결과 AMD는 CES 2026 프레젠테이션(17:20)에 이스터 에그를 숨겨둔 것으로 나타났습니다. 24개의 LPDDR5X 패키지가 있습니다...
View attachment 138387

https://twitter.com/x/status/2013310524109328580

문제는 이 LPDDR5X 패키지용 메모리 컨트롤러가 어디에 있느냐는 것입니다.

미국 특허 US20250098181A1 "통합 메모리 컨트롤러 회로"가 해답일 수 있습니다. 바로 HBM 스택의 맞춤형 베이스 다이에 있는 회로입니다.

만약 그게 사실이라면 LPDDR 패키지는 어디에 있나요?

기질인가요? 불가능할 것 같아요. 거리가 너무 멀어요...
View attachment 138388
아니면 PCB?


View attachment 138391

Thanks, sir
The contents below are custom HBM or custom hbm team
I'm not familiar with this site's style

 

[1250]

I'm using a translator. They firmly believe the HBM controller will be included starting with HBM4E, and other components are similar. The development team seems to have developed their own roadmap, and recently, things like zHBM were included in the plan.
I don't know if it's due to the NDA, but the LPDDR controller isn't included. So, they're saying someone else did what they didn't do. I'll write more slowly.

 

[1250]

I'll write this so that even a complete beginner can understand. HBM is made by stacking the core die on top of the base die. But starting with HBM4E, they thought they could do something with the base die. However, even before they thought about it, AMD was thinking of including an LPDDR controller starting with HBM4. But there are technical limitations that they consider. First, they make the base die themselves, and they match it to the core die. It's true that they're not fundamentally compatible.

 

[1250]

I should also mention the base die process. The base die was originally manufactured using a DRAM process, but starting with 4, it was changed to a logic process. Samsung uses SF4X, Hynix uses TSMC 12nm, and Micron remains the same. As for Micron, they don't use EUV for HBM4. Furthermore, because it's a DRAM process, the maximum performance is low (supplying to NVIDIA is not easy).

 

[1250]

I think I need to rewrite this.
They firmly believe, as engineers, that AMD cannot develop a B-die (I'll abbreviate this from now on; Samsung calls it a buffer) that fits the core dies of the three companies.
They basically think they can only use a single company's C-die. Development costs are also an issue. They assume $100M as the basic development cost.

 

[1250]

I think I need to rewrite this.
They firmly believe, as engineers, that AMD cannot develop a B-die (I'll abbreviate this from now on; Samsung calls it a buffer) that fits the core dies of the three companies.
They basically think they can only use a single company's C-die. Development costs are also an issue. They assume $100M as the basic development cost.

I wrote a lot, but to sum it up, they are of the opinion that custom hbm4 itself is absolutely impossible.

 

[1250]

As I write this, you might be sleeping. Sorry. Jedec exists to solve this problem. Joe Macri, who initiated the development of HBM1, is its chairman. Jedec sets various specifications, particularly physical dimensions (even height). If it plays a significant role, or if it guides, it does. If the requirements are met, the first custom HBM will be commercialized.

If you're curious about their rebuttal, ask me.

 

[marees]

As I write this, you might be sleeping. Sorry. Jedec exists to solve this problem. Joe Macri, who initiated the development of HBM1, is its chairman. Jedec sets various specifications, particularly physical dimensions (even height). If it plays a significant role, or if it guides, it does. If the requirements are met, the first custom HBM will be commercialized.

If you're curious about their rebuttal, ask me.

are we talking of HBM for CDNA 5, which will be out in June this year ?