From what I’ve heard, to stay competitive with Nvidia in data center GPUs, AMD has reallocated many Radeon employees to the data center division to support the rapid update cycle of CDNA and ROCm. Nevertheless, this should not serve as a justification for the delayed progress of RDNA4.
One major upside of NextGen consoles getting prepared is, that there is money from Sony and Microsoft. And AMD has overall much more money than during the times PS5 & Co. were developed. That is a big reason why I assume that RDNA5 will be a decent and quite capable architecture. From what infos, leaks and rumors are suggesting, RDNA5's HW capabilites look on par or even above Blackwell. That is not a bad place to be. With probably two or three especially advanced HW accelerated things (DGF, work graphs, universal compression). The rest will be software (like e.g. FSR).
Yeah sir cdna5 this year
joe is amd's vice president
I'm most curious about AMD's base die process.
I would assume TSMC N3P. Or maybe a Samsung node in case of Samsung HBM? And who knows, if this custom base Die from AMD is real, you could add other things than just additional LPDDR5X memory controllers and PHY. You could add some basic math engines, which is not quite Processing-In-Memory (PIM) but Processing-Near-Memory. The also showcased AXDIMM-PIM would be close to that concept (processing does not happen on the memory Die itself but on a buffer Die). Samsung showed off their PIM tech together with AMD chips (Alveo FPGA & MI100 prototypes) and Samsung is researching the PIM topic together with AMD since at least 2020.
Samsung forciert die Entwicklung von HBM- und DIMM-PIM und zeigt Konzepte, die viel Leistung bei geringem Energiebedarf versprechen.
www.computerbase.de
At Hot Chips 2023, Samsung showed its Processing in/near Memory ranging from PIM-HBM in AMD MI100 test GPUs to LPDDR-PIM and CXL-PNM modules
www.servethehome.com
At ISSCC 2023, Dr. Lisa Su CEO of AMD discusses why stacking compute and DRAM can lead to enormous efficiency gains
www.servethehome.com
Neat:
Those additional math accelerators on the HBM base Die would be available for HBM as well as LPDDR5X memory.
Regarding LPDDR5X I think about stuff like the prefill stage of LLM, where Nvidia uses Rubin CPX as additional accelerator.
But in general, the LPDDR5X controllers and PHY could also be located in the GPU base Die.