Discussion RDNA 5 / UDNA (CDNA Next) speculation

[adroc_thurston]

Looks less like a RDNA4 style tock and more like a clean sheet µarch

1/3/5/7 (every odd tock) is like that.

 

[reaperrr3]

1/3/5/7 (every odd tock) is like that.

That honestly doesn't bode too well, because so far, only the even ones (2 and 4) were actually good.

 

[adroc_thurston]

That honestly doesn't bode too well, because so far, only the even ones (2 and 4) were actually good.

I love superstitions but they just have a roadmap and crank it.
Also RDNA4 sucks balls for obvious reasons.

 

[reaperrr3]

Also RDNA4 sucks balls for obvious reasons.

You mean the lack of halo, or is there something wrong with the uArch itself?
I mean, 64 CUs with GDDR6 virtually matching (and sometimes beating) the 5070Ti is quite alright in my book.
They nearly caught up on a range of issues (V/f, PPW, RT, PT, AI/FSR, mem bw efficiency), and pretty much are slightly ahead on raster IPC for CU vs. SM.

RDNA3 vs. Ada looked FAR worse. Had NV wanted to, they could've priced AMD out of the market then and there.

 

[adroc_thurston]

You mean the lack of halo, or is there something wrong with the uArch itself?

A bit of both.
They cheaped out where they could.

RDNA3 vs. Ada looked FAR worse.

Only in mobile and 3.5 fixed that anyway.

They nearly caught up on a range of issues (V/f, PPW, RT, PT, AI/FSR, mem bw efficiency), and pretty much are slightly ahead on raster IPC for CU vs. SM.

It is indeed a very good shader core; they really haven't shipped any bad ones anyway.

 

[Tigerick]

Hoho, somehow I missed the leak from Chiphell Forum. Just want to add the Universal Compression of RDNA5:

a significant enhancement to reduce memory bandwidth needs by compressing virtually all graphics data, not just textures, enabling faster performance, lower memory requirements for 4K/higher gaming, and boosting upscaling tech like FSR. It works by applying compression across the entire GPU pipeline, leveraging increased silicon speed to overcome traditional performance costs, thereby increasing effective memory bandwidth and improving efficiency for next-gen gaming experiences.

Double SP Per CU + Universal Compression, HOHO

Above table including RDNA5 leaks from MLID with my speculated/missing SKUs with question mark?. As I said AT1 is being cancelled because AT2 full die with faster GDDR7 should be competitive with Rubin-70Ti. Oh yeh, all other OEMs have already implemented 128SP per CU; I really hope you guys do more homework before commenting.

Microsoft is rather paying for 408mm2 wafer than custom designing their own APU cause development cost of 3nm APU costs hundreds of million. Only Sony with high sales volume is able to custom their APU with smaller die area: ~ 280mm2. Hoho, I let you guys think why do I mention these...

One more hint: 7800XT (N32, 60CU) -> 9070XT (N48 XTX full die, 64CU). Why do AMD downgrade the N48 to 70 series?

In conclusion, AMD has only prepared 2 RDNA5 dies: AT0 and AT2 for dGPU lineup and we should forget about mobile GPU lineup. Meanwhile AT3 and AT4 are being used for mGPU with CPU SoC which is selling in laptop for $1500 above, not cheap dGPU. Geez.

Anyhow, RDNA5 lineup going to be mighty impressive as I speculated in Soundwave thread: the Radiance core will be 3 times faster per core, thus AT2-80XT with 64CU's RT should be 2.x times faster than RDNA4's 9070XT (64CU) depending on the clock speed and features.

 

[Win2012R2]

the Radiance core will be 3 times faster per core

Doing exactly what - RT?

 

[Tigerick]

Doing exactly what - RT?

Yep, new term for RT cores.

 

[Win2012R2]

Yep, new term for RT cores.

What makes you think they will be 3x faster per core - about the catch up they need to hit nvidia levels of RT?