Not by that muchhe saying one of AMD sources leak. instead 184 is 144CU?
Not by that muchhe saying one of AMD sources leak. instead 184 is 144CU?
i feel there would be AT1? because too big gap between 64CU and 154CUNot by that much
Yeah i think there should be AT1, because there no 256bus card.hat's a huge hole in the lineup between a 18GB 64CU model and the 36GB 154CU one.
GPU virtualization farms with SRIOV.Market segment - CGVDI?
No, they actually moved a pile of senior technical staff to Radeon recently.And as usual I suspect everything interesting will be killed.
Welp! What does Lisa Su do to the leakers ???It's real but some of the numbers like CU count are slightly wrong (maybe intentionally to find out who leaks this).
NiceNo, they actually moved a pile of senior technical staff to Radeon recently.
Terminate. With prejudice.Welp! What does Lisa Su do to the leakers ???
Kuvaldirovka or perhaps obnuleniye.What does Lisa Su do to the leakers ???
Yeah AT0 should be 192CU and AT2 72CU.It's real but some of the numbers like CU count are slightly wrong (maybe intentionally to find out who leaks this).
Nope, it is great. There is no such thing as a $1k market for dGPU, you either have your halo parts or your $500-$600 market.i feel there would be AT1? because too big gap between 64CU and 154CU
Now this is interesting, I think MALL outside of APUs will only be used for 3D stacked parts as only they have enough compute density to overwhelm GDDR7.Is MALL gone and folded into L2? It's not listed.
I think they are gargantuan SAs instead, 4 SE x 2 SA x 12 WGP for AT0 and 2 SE x 2 SA x 9 WGP for AT2Yeah AT0 should be 192CU and AT2 72CU.
Both only make sense with 3SA/SE.
If we plebs don't get the full fat AT0 for gaming it will be the first time since Vega20, though that was a prosumer part. I think we will depending on where NV ends up.
Not shocked to see a probable H2'27 launch, all those console parts don't tape out or validate themselves.
N3P is whatever, but considering they are going for mono compute+MID N2 would be too yield/cost sensitive. Also 512b for the flagship is absolutely necessary to match NV on memory as otherwise they have easy wins in ML et al.
Nope, it is great. There is no such thing as a $1k market for dGPU, you either have your halo parts or your $500-$600 market.
AT2 is the exact part I was pushing for with RDNA4 had they used GDDR7, great config, the extra 2GB is a big deal.
NV only has that market because of lack of comp pressure, GB203 could be sold for <$700 no problem.
AT0 is a fairly modest halo compared to the moonshot halo's they could've built. Still ~600mm^2 on N3P is a lotta silicon.
Now this is interesting, I think MALL outside of APUs will only be used for 3D stacked parts as only they have enough compute density to overwhelm GDDR7.
Still it appears they are increasing L2 by 4x, so the dynamics will end up somewhere between current AMD L2 and NV L2.
Potentially 2x or more bandwidth with 8x the capacity vs N48 for a moest latency hit would be good enough with 512b GDDR7 for an 8SE/192CU part.
MALL becomes necessary beyond 250CU or so.
Oh no it's not that late.Not shocked to see a probable H2'27 launch, all those console parts don't tape out or validate themselves.
God they sure love changing the ratios and engine org every generation.I think they are gargantuan SAs instead, 4 SE x 2 SA x 12 WGP for AT0 and 2 SE x 2 SA x 9 WGP for AT2
I mean, with how poorly SRAM scales since N5, reducing the combined amount of L2+MALL is one of the easiest area wins, if you can cushion the negative impact on latency and bandwidth efficiency through other means.Now this is interesting
they'll get closer to 3.46 this time.No one, not even AMD, can predict Radeon frequencies.
L2 macro is far bigger, and far less dense.reducing the combined amount of L2+MALL is one of the easiest area wins
Is SE scheduling that much harder than WGP scheduling in each SE to fatten them up that much?I think they are gargantuan SEs instead, 4 SE x 2 SA x 12 WGP for AT0 and 2 SE x 2 SA x 9 WGP for AT2
I sure hope not but the comments are weird unless that is just obfuscation.Oh no it's not that late.
Meanwhile NV in client is just doing mild variations of the same compute hierarchy since Pascal, just pushed further each time.God they sure love changing the ratios and engine org every generation.
This line up has what would be easily a 100 tflops+ gaming GPU. That isn't a hydrogen bomb?finally after that Lisa will hopefully allow them to build the hydrogen bomb.
No, 200CU+, 200TFLOPS+, 200b xtor+ is the hydrogen bomb.This line up has what would be easily a 100 tflops+ gaming GPU. That isn't a hydrogen bomb?
Oh, it may only be seen in Cocytus then. They must have their ML ducks in a row first before trying to sell gamers that sorcery.No, 200CU+, 200TFLOPS+, 200b xtor+ is the hydrogen bomb.
Only possible with a 3D design with MALL.
For example, one possible config is 256CU/4 or 8 SE which would need a little over 3Ghz to get to 200TF, give it 512b G7 and 256MB of MALL below along with Matrix cores in memory and that would be around 200b xtors using ~1k mm^2 of N2/N3 class.Oh, it may only be seen in Cocytus then. They must have their ML ducks in a row first before trying to sell gamers that sorcery.
No that's babymode, not even remotely flexing their 3D integration expertise.That isn't a hydrogen bomb?
FinFlex my beloved.they'll get closer to 3.46 this time.
Yeah the overall area dedicated to cache won't change that much, but this seems to mean a return to de facto 2 cache levels, not a huge shock with RDNA4 being de facto 3 levels down from 4.L2 macro is far bigger, and far less dense.