Discussion RDNA 5 / UDNA (CDNA Next) speculation

[adroc_thurston]

Now with -8CU (-25%), +50% size SE, halved RB and Rasterizer (-50%), no MALL, L2 ?<32MB, LPDDR5X/?LPDDR6 weak memory interface.
1/(-25% WGP (0.75) x +15% freq (1.15)) = +16% IPC when compute bound. Higher in raster games with -50% RB + Rasterizer offset (unless bigger HW).

see assumptions like these are hard for a veeeeery different uarch

 

[MrMPFR]

see assumptions like these are hard for a veeeeery different uarch

I'm just listing the things the weak points (on paper specs) of AT4 based on what has been said so far. Obviously clean slate approach is mandatory.

+15% clk is high end of TSMC node scaling for N3P. +10% clk= 21% higher raster IPC.

Are the number of vector ALUs per WGP/CU vs RDNA4 WGP different? Any other assumptions that need to be changed?

 

[Kepler_L2]

I'm just listing the things the weak points (on paper specs) of AT4 based on what has been said so far. Obviously clean slate approach is mandatory.

+15% clk is high end of TSMC node scaling for N3P. +10% clk= 21% higher raster IPC.

Are the number of vector ALUs per WGP/CU vs RDNA4 WGP different? Any other assumptions that need to be changed?

256 for both but RDNA5 has much fewer dual-issue restrictions.

 

[jpiniero]

Yeah 9060 XT perf at desktop power levels should be possible. For Medusa Premium it would be lower due to power limits and also sharing mem BW with CPU.

That's quite the stretch. Strix Halo is a good 30% slower, and that's with 256-bit@8000.

 

[luro]

https://twitter.com/x/status/2016698967309111356

Dunno wtaf that means

 

[adroc_thurston]

That's quite the stretch. Strix Halo is a good 30% slower, and that's with 256-bit@8000.

This is for discrete option with 192b LP6.

 

[marees]

https://twitter.com/x/status/2016698967309111356

Dunno wtaf that means

he is saying it could be prosumer (inference) rather than gaming

it is not CDNA but RDNA 5 for sure. but despite that it could not be a gaming card — which would be expected to release only in 2027 or later

 

[basix]

So a Rubin CPX competitor from AMD?

 

[jpiniero]

This is for discrete option with 192b LP6.

So it'd be the same as Strix Halo (and much less than the 9060 XT)

 

[adroc_thurston]

So it'd be the same as Strix Halo (and much less than the 9060 XT)

Bandwidth? Yeah.
Perf at 130-150W? No.

 

[jpiniero]

Bandwidth? Yeah.
Perf at 130-150W? No.

It's going to suffocate from lack of bandwidth. Pretty obvious that the marketing's going to entirely be around VRAM. Well, depending on how expensive the 8 GB LPDDR6 is then.

 

[adroc_thurston]

It's going to suffocate from lack of bandwidth.

lmao

Pretty obvious that the marketing's going to entirely be around VRAM.

The marketing is that DT AICs get scraps from someone else's table. neat.

Well, depending on how expensive the 8 GB LPDDR6 is then.

You can't source 8G LP6 on a 192B mem shoreline. 16G is the cutoff.

 

[reaperrr3]

So it'd be the same as Strix Halo (and much less than the 9060 XT)

Don't underestimate how inferior RDNA3(.5) is in terms of bw efficiency vs. RDNA4, let alone RDNA5.

I mean, the 7900 XT already scales worse at 4K than the XTX, meaning even 320bit / 80MB IF$ aren't enough to fully saturate bw at that perf level for RDNA3.

Meanwhile, N48 does more with even less IF$/mem bw, and RDNA5 appears to have several more bw/cache efficiency improvements.

I'd wager the main challenge for desktop AT3/4 will be per-GB-cost of LP5X/LP6 at the planned release window, not bandwidth.

 

[adroc_thurston]

I'd wager the main challenge for desktop AT3/4 will be per-GB-cost of LP5X/LP6 at the planned release window, not bandwidth.

b/w will still be the limitation if you're trying to juice nice and desktop-y 170W+ into AT3 doe.

 

[branch_suggestion]

It's going to suffocate from lack of bandwidth. Pretty obvious that the marketing's going to entirely be around VRAM. Well, depending on how expensive the 8 GB LPDDR6 is then.

Just for the record, AT4 LP6 minimum is 16GB, AT3 is 32GB.
MDSP minimum is realistically 32GB.
LP6 is gonna be a fair bit cheaper per GB than G7.

 

[marees]

Just for the record, AT4 LP6 minimum is 16GB, AT3 is 32GB.
MDSP minimum is realistically 32GB.
LP6 is gonna be a fair bit cheaper per GB than G7.

lpddr6 or lpddr5x for AT4 & MDSP ?

 

[adroc_thurston]

lpddr6 or lpddr5x for AT4 & MDSP ?

This has already been answered

 

[basix]

16GB for AT4 cards would be really good. 32GB for AT3 looks like overkill and really weird when AT2 will feature only 18/24 GByte of GDDR7 memory.

If using LPDDR5X with 12.7 GT/s (Samsung has announced such memory modules):
- 508 GByte/s should be enough for AT3. AT2 with 192bit GDDR7 running at 32 Gbps will have 768 GB/s of bandwidth, so +50% CU and +50% bandwidth would match perfectly
- And then use 16 or 24 GByte for AT3

 

[adroc_thurston]

And then use 16 or 24 GByte for AT3

You can't.
DRAM densities too high to get that on an octachannel.

 

[MrMPFR]

You can't.
DRAM densities too high to get that on an octachannel.

Yeah not happening. Samsung only lists LPDDR5X-10677 x64 at 96-192Gb densities. So 12-24GB x 4 = 48-96GB.

Cadence says LPDDR6 starts at 4GB device densities (x24). 16 of those in AT3 = 64GB. If this is wrong at x48 is device bus width then 32GB is still a lot.

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market tod ay where it’s used in a diverse set of applications that spans

community.cadence.com

 

[T2098]

They certainly do make 512Mx64 (32gbit / 4GiB) LPDDR5X packages though. I've found up to 9600MT/s from Micron, so it's not a huge stretch to think that the 10677 MT/s grade might exist by the time RDNA5 releases.