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Question Raptor Lake - Official Thread

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Hulk

Diamond Member
Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.
 
What if these low end processors come with extra cores compared to their predecessors? That would justify renaming, right?
They Don't

They do have more E cores. The 13500 and 13600 are 6+8 and the 13400 6+4. The i3's look like they are still 4+0.

How is what I replied contradicts what you just posted? It's the "Low End" that will not have any more cores, the low end being i3... every i5 will be Raptor Cove, every i3 13000 will be Alder Cove.
 
I'm curious whether AVX512 is still present in Raptor Cove. My gut feeling says yes.
The Raptor Cove cores in Raptor Lake were built with AVX512, but they are laser Fused now(as in later builds ADL CPUs), the die area space is the same. Intel just being Intel and Segmenting the Market.
 
The Raptor Cove cores in Raptor Lake were built with AVX512, but they are laser Fused now(as in later builds ADL CPUs), the die area space is the same. Intel just being Intel and Segmenting the Market.
That's right, the first ADL launched with AVX512, but got disabled with microcode.
 
From lagging behind in AVX the situation is that Raptor Lake will ship only with AVX2 and Zen 4 with AVX512? My mind can't process this.

Intel really didn't had a choice here?
I doubt this is something that can be "fixed" for the foreseeable future. Atom won't take the overhead of AVX512, and hybrid ISA support is too complicated from the OS side. Seems that AVX512 will remain a server/workstation feature, if not deprecated entirely.
 
I know that AVX512 takes a lot of die space, and specially because of this, couldn't Intel had reworked their FPU to create something much smaller that still supports AVX512 with lower performance?
Even Zen 4c will have AVX512.
I know it's "niche" but Intel allowing the competitor to brag about having a more "robust" ISA? Allowing their mind share slip away like this?
 
I know that AVX512 takes a lot of die space, and specially because of this, couldn't Intel had reworked their FPU to create something much smaller that still supports AVX512 with lower performance?
Even Zen 4c will have AVX512.
I know it's "niche" but Intel allowing the competitor to brag about having a more "robust" ISA? Allowing their mind share slip away like this?

The 8+16 Raptor Lake die is big enough as it is. Plus you have to factor in time to market... Intel's just going to have to eat this one.

I doubt this is something that can be "fixed" for the foreseeable future. Atom won't take the overhead of AVX512, and hybrid ISA support is too complicated from the OS side. Seems that AVX512 will remain a server/workstation feature, if not deprecated entirely.

It's going to get added to the Atom cores at some point.
 
I know that AVX512 takes a lot of die space, and specially because of this, couldn't Intel had reworked their FPU to create something much smaller that still supports AVX512 with lower performance?
Even Zen 4c will have AVX512.
I know it's "niche" but Intel allowing the competitor to brag about having a more "robust" ISA? Allowing their mind share slip away like this?
They could have done it like in Tiger Lake, one AVX512 FPU Register. But then they would have have to redesign the Golden/Raptor Cove/Redwood Cove for each segment(Server and Client), but it's cheaper to design one single core and just segment it.

1662741010975.png


And get this.... That design is set in Stone for the next years.

Golden Cove vs Meteor Lake FPU design.

1662741510156.png
 
They could have done it like in Tiger Lake, one AVX512 FPU Register. But then they would have have to redesign the Golden/Raptor Cove/Redwood Cove for each segment(Server and Client), but it's cheaper to design one single core and just segment it.

The Atom cores are the problem.
 
I must say I will be a little bit pissed off when they will sell my 12600K renamed for half the price. Perhaps it will have slower boost.
That is pretty typical for chips when the next generation comes out. No specific chip model get price cuts, but they often get a new name, a new tier, and a new price. Sometimes it is the exact same specifications, but one tier lower (like an i5 chip becomes an i3 with i3 pricing). This time it looks like the closest thing to the 12600K might be the 13400 without overclocking ability and a 300 MHz turbo speed cut. But the price will be quite a bit cheaper (~1/3rd less). Alternatively, for about the same price you paid the 13600K will be 200 MHz faster have 4 more E cores, and a few bells/whistles.
 

At 4.9, the 12900K gets 15344 ( 6P/12T ) and at 5.5 should get close to 17200

Cinebench likes the whole 30 MiB Cache available on the 12900K, Alder Lake with Smaller total L3 Cache allowed per CPU will have lower MT Performance.

1662749927468.png

Intel i9 12900K 6C/12T with 30 MiB L3$ @5.1 Ghz: 15,970 Points

Intel i5 12400 6C/12T with 18MiB L3$ @5.1 Ghz: 14,789 Points(8% lower than 12900K at ISO Speed and ISO Cores/Threads)


The issue is compounded in this extreme case...

1662750807945.png

It's not so much that Cinebench loves Extra Cache, but that Golden Cove gets better performance the more L3 Cache you feed it. The Poor Celeron is Starved with only 4MiB of total system.
 
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The 8+16 Raptor Lake die is big enough as it is. Plus you have to factor in time to market... Intel's just going to have to eat this one.



It's going to get added to the Atom cores at some point.

As previously announced, as the successor to Intel’s existing Knights Corner (1st generation Xeon Phi), Knights Landing makes the jump from using Intel’s enhanced Pentium 1 (P54C) x86 cores to using the company’s modern Silvermont x86 cores, which currently lie at the heart of the Intel’s Atom processors. These Silvermont cores are far more capable than the older P54C cores and should significantly improve Intel’s single threaded performance. All the while these cores are further modified to incorporate AVX units, allowing AVX-512F operations that provide the bulk Knights Landing’s computing power and are a similarly potent upgrade over Knights Corner’s more basic 512-bit SIMD units.
source:
 
Cinebench likes the whole 30 MiB Cache available on the 12900K, Alder Lake with Smaller total L3 Cache allowed per CPU will have lower MT Performance.

View attachment 67366

Intel i9 12900K 6C/12T with 30 MiB L3$ @5.1 Ghz: 15,970 Points

Intel i5 12400 6C/12T with 18MiB L3$ @5.1 Ghz: 14,789 Points(8% lower than 12900K at ISO Speed and ISO Cores/Threads)


The issue is compounded in this extreme case...

View attachment 67367

It's not so much that Cinebench loves Extra Cache, but that Golden Cove gets better performance the more L3 Cache you feed it. The Poor Celeron is Starved with only 4MiB of total system.

No, Cinebench do not care too much about L3 Cache size or system memory speed.

As an example take these two Zen 2 processors, because of the very big difference in L3 cache size.There are plenty of applications that do not burden/not need the large L3 cache.

R5 4650G, 8mb L3 Cache

R5 3600, 32mb L3 Cache






As you see, monolithic Renoir APU is still a faster processor in several cases.

Gaming comparison with discrete GPU, there is a big difference(not always)between the size of the L3 cache.
 
No, Cinebench do not care too much about L3 Cache size or system memory speed.
No, but Golden Cove Clearly chokes when it only has 2 MiB per core as clearly seen on the Benchmark I posted(If you would like to dispute that you can take that with techspot)


As an example take these two Zen 2 processors, because of the very big difference in L3 cache size.There are plenty of applications that do not burden/not need the large L3 cache.
That just shows that AMD Built Zen with plenty of Cache.
 
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