Question Raptor Lake - Official Thread

[Hulk]

Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.

 

[controlflow]

Would you stop spamming this thread with your nonsense nonsense gibberish?? I am about to report you for derailing this thread.

You should probably take a break for a bit.

Somehow you think its ok for you to be spamming about PBO 5950x results and making up 7950x results that don't exist but suddenly you find it offensive that other people are having a relevant discussion by comparing upcoming Intel and AMD chipsets and discussing power limits.

 

[Abwx]

This is assuming Raptor Lake has the exact same power scaling as Alder Lake, which by all accounts isn't true. Raptor Lake will have better performance per watt than Alder Lake (likely through node tweaks), which is why they are increasing core count and frequency.

They can improve the node but they are squeezing the last drop of frequency, the higher clocks will inherently render it no more efficient than ADL.

 

[IntelUser2000]

Would you stop spamming this thread with your nonsense nonsense gibberish?? I am about to report you for derailing this thread.

You aren't doing better. You should listen to your own advice.

Alderlake's PL2 is 241W per Intel. And Raptorlake leak showed 253W. No one cares about PL4.

They can improve the node but they are squeezing the last drop of frequency, the higher clocks will inherently render it no more efficient than ADL.

This isn't false but the numbers you put out are speculation. The thing I talk about how there's too much focus on tech not the people? Well this is one. People calling names and throwing insults for a computer chip! Imagine what our ancestors would think. It's not that important. Wait for reviews.

 

[Carfax83]

Yep, this. Probably not node tweaks, but maybe better yields let them bin chips for lower voltage, probably what you mean. Cores will also require a few watts less when accessing memory (since they’ll spend more time in L2), and there could be a number of IMC and other uncore tweaks to further reduce power consumption. We’ll see. Rumors could also be wrong and they really do target 300W or more, but that would be a disaster both in terms of lack of support from 12th gen mobos that have weaker power delivery, and in terms of heat generation (and presumably mobile battery life).

I don't know, I doubt better binning and yields could account for the large boost in frequencies as well as increasing core counts. The reason why I said node tweaks is because Intel historically, has shown great expertise when it comes to squeezing more performance out of existing nodes.

DLVR may also be a wild card in this as well. I'm hopeful that Intel will disclose more information about Raptor Lake on its architecture day later this month.

 

[IntelUser2000]

I don't know, I doubt better binning and yields could account for the large boost in frequencies as well as increasing core counts. The reason why I said node tweaks is because Intel historically, has shown great expertise when it comes to squeezing more performance out of existing nodes.

DLVR may also be a wild card in this as well. I'm hopeful that Intel will disclose more information about Raptor Lake on its architecture day later this month.

Binning and process isn't the only thing for CPUs you know? Circuitry can be better optimized. The package itself can be improved. Refreshes typically put out 100-200MHz without downsides without process changes. There's a reason it's not called Intel 6 or Intel 7+. Seems that's what Raptorlake is.

DLVR won't help at these extreme frequencies.

 

[Carfax83]

They can improve the node but they are squeezing the last drop of frequency, the higher clocks will inherently render it no more efficient than ADL.

This maybe true, so I guess we'll have to wait and see. Though I have a hard time believing that Intel would boost clock speeds to near 6ghz as well as doubling the efficiency cores if they didn't have some kind of plan or method to control the outrageous power consumption and heat output that would result.

As I said above, DLVR may be a wild card that could have some impact. Only time will tell.

 

[Carfax83]

DLVR won't help at these extreme frequencies.

One can dream. It would be cool if Intel did find a way to reduce the motherboard's excessive VRM voltages however with no conscious input from the owner. That alone could reduce power consumption and heat significantly, as seen by the numerous examples we have of undervolting.

 

[IntelUser2000]

One can dream. It would be cool if Intel did find a way to reduce the motherboard's excessive VRM voltages however with no conscious input from the owner. That alone could reduce power consumption and heat significantly, as seen by the numerous examples we have of undervolting.

Yes if you can characterize every workload and have a database to refer to. Or, you can just undervolt, or even disable Turbo or buy a T chip.

The voltage droop happens because no power source is an ideal source, and it's represented with an imaginary tiny value resistor. So when the current requirements rise with a high load, voltage drop happens across that "resistor" according to V=IR. The drop is lower when your power source can deliver more power.

There's no simple way around this. Pretty much the other way is to predict the future with 100% accuracy and the computer knowing in advance exactly what you are going to do.

You know if they found an easier way to do that they'll use that to increase performance even more.

You have an option, way more than before, just not if you want to have xx900K and use 1W. I am looking to replace this XPS 12 with Y chip based used convertible. I should be able to get 12-15 hours of battery life with the optimizations I am going to put into it using a 45WHr battery.

 

[shady28]

Binning and process isn't the only thing for CPUs you know? Circuitry can be better optimized. The package itself can be improved. Refreshes typically put out 100-200MHz without downsides without process changes. There's a reason it's not called Intel 6 or Intel 7+. Seems that's what Raptorlake is.

DLVR won't help at these extreme frequencies.

There's been a complete rework of L1 and L2 cache. I would imagine the IMC is heavily updated too. Given the scaling of Alder Lake with higher and higher DDR5 frequencies, this may have been all they needed to do to get more "IPC", and we would never know the difference since most of these tests don't really test true IPC of a core. You'd have to run something that fits in L1 cache on a single tasking OS similar to MS-DOS to really do an core IPC test.

This is an 8P/8E 12900K vs 8P/8E 13700K - cache differences :

 

[Carfax83]

There's been a complete rework of L1 and L2 cache. I would imagine the IMC is heavily updated too. Given the scaling of Alder Lake with higher and higher DDR5 frequencies, this may have been all they needed to do to get more "IPC", and we would never know the difference since most of these tests don't really test true IPC of a core. You'd have to run something that fits in L1 cache on a single tasking OS similar to MS-DOS to really do an core IPC test.

This is an 8P/8E 12900K vs 8P/8E 13700K - cache differences :


View attachment 65487

Wow, that's the first time I'm seeing that. I can't believe no one in the media picked up on that before.

 

[IntelUser2000]

@shady28

By the way Geekbench is confused about E vs P cores for caches. Those are not Raptor vs Alder differences.

E cores have a larger Instruction cache and P cores have a larger Data cache for L1. 4MB L2 is for RPL E cores and 1.25MB Is ADL P core L2. So what that compares is Alderlake's P cores vs Raptorlake's E cores.

There's been a complete rework of L1 and L2 cache. I would imagine the IMC is heavily updated too. Given the scaling of Alder Lake with higher and higher DDR5 frequencies, this may have been all they needed to do to get more "IPC", and we would never know the difference since most of these tests don't really test true IPC of a core. You'd have to run something that fits in L1 cache on a single tasking OS similar to MS-DOS to really do an core IPC test.

Oh no... are you suggesting we all use Dhrystone?!

That's why I hate the term IPC. It confuses the heck out of people. Then we have silly arguments about x86 vs ARM instructions and cache hits and all that nonsense. The term I use is performance per clock, which kills any obfuscation. It applies to any and every processor regardless.

We are talking about single digit percentages. So we wait for reviews.

 

[pakotlar]

There's been a complete rework of L1 and L2 cache. I would imagine the IMC is heavily updated too. Given the scaling of Alder Lake with higher and higher DDR5 frequencies, this may have been all they needed to do to get more "IPC", and we would never know the difference since most of these tests don't really test true IPC of a core. You'd have to run something that fits in L1 cache on a single tasking OS similar to MS-DOS to really do an core IPC test.

This is an 8P/8E 12900K vs 8P/8E 13700K - cache differences :


View attachment 65487

I didn’t realize L1 was adjusted. That could have a big impact; wonder how that squares with Raptor Lake getting a larger performance bump from DDR5 than Alder Lake; I’d expect with more cache memory subsystem impact to be smaller, much like 5800X 3D doesn’t benefit from faster memory as much as 5800X. Maybe the DDR5 IMC was redesigned; there was some suspicion that it was present mainly for compat in ADL.

 

[IntelUser2000]

I didn’t realize L1 was adjusted. That could have a big impact; wonder how that squares with Raptor Lake getting a larger performance bump from DDR5 than Alder Lake; I’d expect with more cache memory subsystem impact to be smaller, much like 5800X 3D doesn’t benefit from faster memory as much as 5800X. Maybe the DDR5 IMC was redesigned; there was some suspicion that it was present mainly for compat in ADL.

That's false data. Refer to my post above.

 

[shady28]

By the way Geekbench is confused about E vs P cores for caches. Those are not Raptor vs Alder differences.

E cores have a larger Instruction cache and P cores have a larger Data cache for L1. 4MB L2 is for RPL R cores and 1.25MB Is ADL P core L2.



Oh no... are you suggesting we all use Dhrystone?!

That's why I hate the term IPC. It confuses the heck out of people. Then we have silly arguments about x86 vs ARM instructions and cache hits and all that nonsense. The term I use is performance per clock, which kills any obfuscation. It applies to any and every processor regardless.

We are talking about single digit percentages. So we wait for reviews.

I think we're in agreement, the term IPC is being used by the community to imply how many instructions an entire package can do - not just the CPU. It includes core, cache, memory controller, and memory - including all those latencies and bandwidth. The real meaning of IPC is not tested, yet people talk about "IPC" increases.

This is a good example - a benchmark of some low level machine code instructions. It's interesting because, there are some instructions that run faster on a Phenom II than on modern CPUs.

GitHub - TheRainDoodle/Phenom-II-Benchmark: Small set of low level benchmarks for testing hardware speed against a Phenom II 810 Quad Core

Small set of low level benchmarks for testing hardware speed against a Phenom II 810 Quad Core - TheRainDoodle/Phenom-II-Benchmark

github.com

"I was surprised and fascinated by the results. There are many things the old Phenom does much faster than my modern CPU, although they are generally single threaded, and these tests do not currently appear in the benchmark. Modern CPU's have larger SIMD registers and more cores, but are otherwise not much faster."

 

[shady28]

That's false data. Refer to my post above.

"Intel hasn't shared the names of the chip microarchitectures that it will etch onto the Intel 7 node for the Raptor Lake CPUs, but rumors indicate the P-Cores will use 'Raptor Cove' naming while the E-Cores will stick with Gracemont. However, both cores do have significantly more L2 cache, suggesting a re-working of the underlying designs. "

...

"Intel has increased per-core L2 cache capacity for both the P-Cores and the E-Cores. The E-Cores see an increase to 2MB of private L2 cache per core, a 60% increase over the 1.25 MB per core found in Alder Lake. Intel also boosted the amount of L2 cache shared among each quad-core cluster of E-Cores to 4 MB, a doubling over the 2MB with Alder Lake. That means we'll see up to 32MB of L2 cache. "

https://www.tomshardware.com/news/intel-13th-gen-raptor-lake-release-date-specifications-pricing-benchmarks-all-we-know-specs

 

[pakotlar]

"Intel hasn't shared the names of the chip microarchitectures that it will etch onto the Intel 7 node for the Raptor Lake CPUs, but rumors indicate the P-Cores will use 'Raptor Cove' naming while the E-Cores will stick with Gracemont. However, both cores do have significantly more L2 cache, suggesting a re-working of the underlying designs. "

...

"Intel has increased per-core L2 cache capacity for both the P-Cores and the E-Cores. The E-Cores see an increase to 2MB of private L2 cache per core, a 60% increase over the 1.25 MB per core found in Alder Lake. Intel also boosted the amount of L2 cache shared among each quad-core cluster of E-Cores to 4 MB, a doubling over the 2MB with Alder Lake. That means we'll see up to 32MB of L2 cache. "

https://www.tomshardware.com/news/intel-13th-gen-raptor-lake-release-date-specifications-pricing-benchmarks-all-we-know-specs

IntelUser was referring to the L1. The L2 increase isnt under dispute.

 

[shady28]

IntelUser was referring to the L1. The L2 increase isnt under dispute.

I see, my bad.

 

[nicalandia]

Double post

 

[nicalandia]

There's been a complete rework of L1 and L2 cache. I would imagine the IMC is heavily updated too.

Wow, that's the first time I'm seeing that. I can't believe no one in the media picked up on that before.

That information was from a QS sample and Geekbench not detecting the actual data correctly.

The L1 data still the same from Alder Lake(L1 Instruction and L1 Data Cache, the one posted by shady28 had the wrong info posted by GB5 due to QS sample)

Retail 13900K Geekbench L1/L2 data



Comparison with Alder Lake

 

[DrMrLordX]

But no, cinebench and pov-ray are like the first thing up on every review.

He wasn't talking about POV-Ray. At least they are good FP benchmarks, which is why they became popular in the first place. Though they are not the only benches I want to see, I'd much rather see them than Geekbench since it doesn't mirror anything I do.

 

[Shmee]

Hello all, due to some previous altercations in this thread, a warning here. Please keep the subject matter on Raptor Lake. AMD CPUs/chipsets and other tech can be discussed in another thread. And the bickering needs to stop. If you suspect someone of breaking rules or trolling, do not engage, but please report the content. Further instances of bickering or other problematic posting may be met with infractions. Thanks,

AT Mod Shmee

 

[shady28]

13700K, looks stock clocked with DDR5-5200. This one leaked on July 23 :

Z690 Steel Legend WiFi 6E/D5 - Geekbench

Benchmark results for a Z690 Steel Legend WiFi 6E/D5 with an Intel Core i7-13700K processor.

browser.geekbench.com

 

[shady28]

13600K vs my best 10850K run (slight OC and memory tune) :

 

[IntelUser2000]

IntelUser was referring to the L1. The L2 increase isnt under dispute.

L2 data is wrong too. Because with Alderlake it's referring to P cores, but with Raptorlake it's suddenly referencing E cores.

 

[IntelUser2000]

I think we're in agreement, the term IPC is being used by the community to imply how many instructions an entire package can do - not just the CPU. It includes core, cache, memory controller, and memory - including all those latencies and bandwidth. The real meaning of IPC is not tested, yet people talk about "IPC" increases.

90% do, but the few don't.

Heck it stands for Instructions Per Clock. Hence the confusion. Performance per clock confuses nobody. And it doesn't care things like memory or cache, it's all taken into account. It's arguing about horsepower versus top speed/acceleration/towing capacity. The latter is what really matters.

AMD and Intel also does silly things like 19% gain. Really? Are you sure it's not 18.5% or 20%? In the sane days they used to say 15-20%. I am going to outdo your 19% with 21%.

Give me a break, seriously.