NTMBK
Lifer
- Nov 14, 2011
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ShintaiDK said:Memory seems to be 6 channels. Only adds to the question what all those pins are needed for.
3000 pins would be about right for 6 channels no? Given that 2011 gives you 4 channels.
ShintaiDK said:Memory seems to be 6 channels. Only adds to the question what all those pins are needed for.
i wonder if big data customers with CPU needs in the 100s of thousands+ get invited to intel to give input as to what they want to see out of a server CPU? similar to how boeing (and i'm sure airbus) invites their big customers early on in the design process of an airplane?
3000 pins would be about right for 6 channels no? Given that 2011 gives you 4 channels.
Does the customization go beyond TDP to things like IO configuration?They do. Even custom SKUs are made.
There must be a lot more than that. Like Ethernet, I/O, Storage etc. Xeon D style I think.
I think it will be difficult to top intel's server efforts at 28nm. Even with all those cores, they are much weaker than haswell cores.
In development for more than two years, the SDP includes a custom server-class 24-core SoC built using advanced FinFet technology.
Does the customization go beyond TDP to things like IO configuration?
I'm also thinking about something on a more basic level than that. Something at the architecture or instruction level
More like 'this is the type of data we need to process and the algorithms to do it. What can you do to help us?'
Kitguru claims that Purley (Intel's 6-channel DDR4 platform) will have "up to" 3467 pins: http://www.kitguru.net/components/c...s-to-support-6tb-of-dram-use-3467-pin-socket/
My understanding is that Intel can provide different turbo speed, L3 sizes and number of cores to some customers.Intel's processor design efforts are cloistered and are not influenced by anybody but intel's executives and shareholders. The best that Apple, arguably the most powerful company on earth, could do in influencing intel's processor ambitions was to get Iris/Iris pro. Hardly the kind of low-level collaboration you see with partners such as nvidia/auto and qualcomm/android vendors.
i wonder if big data customers with CPU needs in the 100s of thousands+ get invited to intel to give input as to what they want to see out of a server CPU? similar to how boeing (and i'm sure airbus) invites their big customers early on in the design process of an airplane?
Do you have a reference for that?You can get instructions too.
Do you have a reference for that?
We are definitely doing all of the above," confirmed Jason Waxman, general manager of Intel's Cloud Infrastructure Group.
"As far as the etching goes, we have done different things for different customers, and we have put different things into the silicon, such as adding instructions or pins or signals for logic for them. The difference is that it goes into all of the silicon for that product. And so the way that you do it is somebody gives you a feature, and they say, 'Hey, can you get this into the product?' You can't do something that takes up a huge amount of die, but you can do an instruction, you can do a signal, you can do a number of things that are logic-related."
It's not 28nm:
24-cores on a 14/16nm process, fed by 6 channels of DDR4, at ~140W TDP. For comparison Skylake-EP is going to be up to 28 cores, also fed by 6 channels of DDR4, and obviously also on 14nm. This should hopefully be an interesting fight, though obviously Intel has the software maturity advantage.
Thanks. Now I wonder how the customers will handle the pain of having extra instructions only supported on some chips and most likely supported by no tool except perhaps the buggy icc.
Thanks. Now I wonder how the customers will handle the pain of having extra instructions only supported on some chips and most likely supported by no tool except perhaps the buggy icc.
Thanks. Now I wonder how the customers will handle the pain of having extra instructions only supported on some chips and most likely supported by no tool except perhaps the buggy icc.
Intel's processor design efforts are cloistered and are not influenced by anybody but intel's executives and shareholders. The best that Apple, arguably the most powerful company on earth, could do in influencing intel's processor ambitions was to get Iris/Iris pro. Hardly the kind of low-level collaboration you see with partners such as nvidia/auto and qualcomm/android vendors.
My understanding is that Xeon have all features enabled as far as ISA goes (might be wrong, Intel can be so utterly stupid with ISA segmentation), and that Intel plays, as I wrote above, with frequency, cores and LLC (which also means TDP changes).I'm taking this two year old Register article with some serious salt. The "added instructions" that the Intel quote refers to may very well simply be the usual ISA extensions that wouldn't normally be present in combination with other features they want on a standard SKU.
I doubt it too. OTOH they surely talk with higher end partners to define new ISA extensions that will be available to others. Perhaps these extensions are first available to some privileged customers, but even that is doubtful.I really doubt they're allocating new chunks of the opcode space and new opcode functionality at customer request.
Also, the 24-core SKU is a prototype, they plan to have more cores.
3000 pins would be about right for 6 channels no? Given that 2011 gives you 4 channels.
Does the customization go beyond TDP to things like IO configuration?
I'm also thinking about something on a more basic level than that. Something at the architecture or instruction level
More like 'this is the type of data we need to process and the algorithms to do it. What can you do to help us?'