processor size, features, and speed...why do they limit themselves?

[MrDudeMan]

lets just use Intel for this thread. nothing against amd, but people that know a lot about intel chips frequent this forum, so yeah.


why do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

i dont understand why a CPU cant do what a GPU does. ive read a few articles and threads regarding this issue, but im not satisfied. can someone please shed some light on why it cant all be integrated into 1? im sure it would be very complex, and bad for the gamer because of increased requirements for games...but, wouldnt it still be better for most workstations and non-gaming consumers?

maybe that idea is not feasible...ok, i can handle that. however, when new technologies that influence the speed (read: not mhz, pure processing potential), why cant it be added to the die but not decrease its size? i will admit, i have no idea if the size or shape of the processor change greatly, but it seems like they are much smaller than they used to be. would it hinder performance for it to remain that same physical size while the transistors continue to improve in both size and design?

 

[Matthias99]

Originally posted by: MrDudeMan
lets just use Intel for this thread. nothing against amd, but people that know a lot about intel chips frequent this forum, so yeah.

why do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

Why would you NOT want to reduce the size? Smaller size = smaller distance between parts = higher clock rate (everything else being equal). It also means more dies/silicon wafer, which = cheaper chips.

i dont understand why a CPU cant do what a GPU does. ive read a few articles and threads regarding this issue, but im not satisfied. can someone please shed some light on why it cant all be integrated into 1? im sure it would be very complex, and bad for the gamer because of increased requirements for games...but, wouldnt it still be better for most workstations and non-gaming consumers?

A GPU is basically a massively parallel hardwired fixed-function vector processor that does 3D rendering calculations, and nothing else. There are some programmable elements (pixel/vertex shaders, HWT&L, etc.) in cards made in the last few years, but you could not run a 'normal' program on a GPU.

A CPU is a general-purpose processing unit that does all kinds of operations on data, and cannot make any assumptions about what instructions it will be asked to do next. You CAN do 3D rendering on a CPU; it's just painfully slow compared to a modern dedicated GPU.

maybe that idea is not feasible...ok, i can handle that. however, when new technologies that influence the speed (read: not mhz, pure processing potential), why cant it be added to the die but not decrease its size? i will admit, i have no idea if the size or shape of the processor change greatly, but it seems like they are much smaller than they used to be. would it hinder performance for it to remain that same physical size while the transistors continue to improve in both size and design?

Huh? Your question makes no sense (or I'm not understanding). If you kept the gate length the same and added more stuff, the die would get bigger, which would slow it down (because of more distance between the parts, etc.) You want it to be as small as physically possible, generally.

 

[Gibsons]

I think the OP is suggesting that when you move to X percent smaller process, why not add X percent more transistors/features/cache, keeping the whole chip the same original size.

 

[Matthias99]

Originally posted by: Gibsons
I think the OP is suggesting that when you move to X percent smaller process, why not add X percent more transistors/features/cache, keeping the whole chip the same original size.

Well, you *could*, but this would at least partially negate the speed benefits of a smaller chip/gate length, and would eliminate the yield benefits of a smaller chip/process.

In many cases, though, chips do get some new features, optimizations, etc. at the same time as a process shrink (although this last generation of CPUs didn't gain any features doing so; both AMD and Intel just did a straight die shrink). For example, when ATI went from the R300/350/360 (130nm) to the RV350 (110nm) GPU cores, they also added some new hardware to do adaptive trilinear filtering.

 

[TuxDave]

Damn... you answered all the questions pretty quick. There's nothing left for me. I could add a little more too. Yes, smaller dies will yield more dies per wafer making it cheaper, but there's also a yield issue. The larger the die, the higher the probability of failure for a given speed target.

 

[MrDudeMan]

Originally posted by: Matthias99

Originally posted by: MrDudeMan
lets just use Intel for this thread. nothing against amd, but people that know a lot about intel chips frequent this forum, so yeah.

why do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

Why would you NOT want to reduce the size? Smaller size = smaller distance between parts = higher clock rate (everything else being equal). It also means more dies/silicon wafer, which = cheaper chips.

but clock rate isnt that important anymore it seems. if it had more raw power, then who cares if it is clocked a tad bit slower. id imagine leaving the die the same size wouldnt steal many mhz from the total, but would massively increase transistor count.

i dont understand why a CPU cant do what a GPU does. ive read a few articles and threads regarding this issue, but im not satisfied. can someone please shed some light on why it cant all be integrated into 1? im sure it would be very complex, and bad for the gamer because of increased requirements for games...but, wouldnt it still be better for most workstations and non-gaming consumers?

A GPU is basically a massively parallel hardwired fixed-function vector processor that does 3D rendering calculations, and nothing else. There are some programmable elements (pixel/vertex shaders, HWT&L, etc.) in cards made in the last few years, but you could not run a 'normal' program on a GPU.

A CPU is a general-purpose processing unit that does all kinds of operations on data, and cannot make any assumptions about what instructions it will be asked to do next. You CAN do 3D rendering on a CPU; it's just painfully slow compared to a modern dedicated GPU.

gotcha. thanks.

maybe that idea is not feasible...ok, i can handle that. however, when new technologies that influence the speed (read: not mhz, pure processing potential), why cant it be added to the die but not decrease its size? i will admit, i have no idea if the size or shape of the processor change greatly, but it seems like they are much smaller than they used to be. would it hinder performance for it to remain that same physical size while the transistors continue to improve in both size and design?

Huh? Your question makes no sense (or I'm not understanding). If you kept the gate length the same and added more stuff, the die would get bigger, which would slow it down (because of more distance between the parts, etc.) You want it to be as small as physically possible, generally.

for not understanding my question, you sure answered it pretty well read my response to your first statement...i think it applies to this also (maybe?).

 

[MisterChief]

OMG. does it really matter? processors will keep getting smaller, performance will increase, and we can all live happier lives to the Xth percentage. You sleep, you eat, you screw, your happy, you GET ON WITH LIFE!

PS- lol, jk

 

[Tab]

As I understand it, when we have samller die's we use less of the silicon wafer... Not exactly sure how that works as you'd think with all the stuff that is put onto the wafers takes up more space.... As I understand it, companies get more products out of their wafers... You would think electricity is already moving fast enough that's it's not really a issuse... Kind of curious how we got the idea to use silicon and make nice big wafer out of them...

It seems that GPU are made for graphics programs or just to do graphics and not have other cpu operations... I would assume you could in theory make a CPU do the same graphics orienated stuff right? We just really haven't made a programing language for it right? (Though I've heard of Apple's Quartz)

 

[TuxDave]

Originally posted by: MrDudeMan

Originally posted by: Matthias99

Originally posted by: MrDudeMan
lets just use Intel for this thread. nothing against amd, but people that know a lot about intel chips frequent this forum, so yeah.

why do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

Why would you NOT want to reduce the size? Smaller size = smaller distance between parts = higher clock rate (everything else being equal). It also means more dies/silicon wafer, which = cheaper chips.

but clock rate isnt that important anymore it seems. if it had more raw power, then who cares if it is clocked a tad bit slower. id imagine leaving the die the same size wouldnt steal many mhz from the total, but would massively increase transistor count.

Umm... that's what Intel has been doing? The core may have shrunk by 20% or so but it's has orders of magnitude more transistors. Hell, Intel just released a server processor containing 1.7 BILLION transistors. BILLIONS!!!!

 

[MrDudeMan]

Originally posted by: MisterChief
OMG. does it really matter? processors will keep getting smaller, performance will increase, and we can all live happier lives to the Xth percentage. You sleep, you eat, you screw, your happy, you GET ON WITH LIFE!

PS- lol, jk

:laugh:

Originally posted by: Tabb
As I understand it, when we have samller die's we use less of the silicon wafer... Not exactly sure how that works as you'd think with all the stuff that is put onto the wafers takes up more space.... As I understand it, companies get more products out of their wafers... You would think electricity is already moving fast enough that's it's not really a issuse... Kind of curious how we got the idea to use silicon and make nice big wafer out of them...

It seems that GPU are made for graphics programs or just to do graphics and not have other cpu operations... I would assume you could in theory make a CPU do the same graphics orienated stuff right? We just really haven't made a programing language for it right? (Though I've heard of Apple's Quartz)

you and i are thinking pretty similar thoughts...i just wish i knew more about this stuff right now.

Originally posted by: TuxDave

Umm... that's what Intel has been doing? The core may have shrunk by 20% or so but it's has orders of magnitude more transistors. Hell, Intel just released a server processor containing 1.7 BILLION transistors. BILLIONS!!!!

well, thats why i asked this question. i didnt know that.

 

[TuxDave]

Originally posted by: MrDudeMan

Originally posted by: MisterChief
OMG. does it really matter? processors will keep getting smaller, performance will increase, and we can all live happier lives to the Xth percentage. You sleep, you eat, you screw, your happy, you GET ON WITH LIFE!

PS- lol, jk

:laugh:

Originally posted by: Tabb
As I understand it, when we have samller die's we use less of the silicon wafer... Not exactly sure how that works as you'd think with all the stuff that is put onto the wafers takes up more space.... As I understand it, companies get more products out of their wafers... You would think electricity is already moving fast enough that's it's not really a issuse... Kind of curious how we got the idea to use silicon and make nice big wafer out of them...

It seems that GPU are made for graphics programs or just to do graphics and not have other cpu operations... I would assume you could in theory make a CPU do the same graphics orienated stuff right? We just really haven't made a programing language for it right? (Though I've heard of Apple's Quartz)

you and i are thinking pretty similar thoughts...i just wish i knew more about this stuff right now.

Originally posted by: TuxDave

Umm... that's what Intel has been doing? The core may have shrunk by 20% or so but it's has orders of magnitude more transistors. Hell, Intel just released a server processor containing 1.7 BILLION transistors. BILLIONS!!!!

well, thats why i asked this question. i didnt know that.

Oh.... ok. Well, for future information, when Intel releases a new process shrink, everything will take up roughly half the previous area. It doesn't quite apply as nicely in modern technology since scaling is really getting rough. So if you think about how many times Intel has released a smaller transistor, if they kept everything the same, we'd have this puny dot of a processor.

 

[pm]

Originally posted by: MrDudeMan
lwhy do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

Aside from the things that Matthias wrote - which were all correct - they are actually slowly getting bigger. I have been working on Montecito - an upcoming member of the Itanium processor family. It has 1.75 billion transistors and the die size is the largest that I am aware of.

The problem with increasing die size is everything matthias mentioned as well as yield and power. You can only cool so many watts coming off of a chip - and each transistor will leak a certain amount of power (an amount that is increasing with each generation of process technology...) so if you increase your transistor count by 30% than you are also increasing the amount of power that is consumed by leakage by an equivalent amount, which hurts your overall power budget for the processor.

Yield is probably the primary concern. Imagine that you are scattering about 50 grains of sand over a 12" wafer. Each grain symbolizes a flaw - a bit of dust, a bubble in the photoresist, something. Now if you had one chip the size of the wafer (which isn't possible, but for the sake of arguement)... you'd have 50 errors on that chip and you would have zero yield on the wafer. You would pretty much never ever get a working chip. Now imagine that you have 50 chips on the wafer... well, each time it's likely that those grains of sand fall on the wafer that a few of the chips would somehow manage to avoid having one... and if you had 500, then you'd have 450 working chips... or even more. So clearly there is a huge benefit to he bottom line of the company in having the chip be fairly small... not only can you get more per wafer, but more are likely to work. The numbers are made up, but the analogy is close enough to real life.

Why is Montecito so huge? Most of the chip is cache - in excess of 24MB of cache - and there are mechanisms in place to replace bad cache lines... so if an error shows up in the cache, it can be fixed. And for power, well, there will be a lot of details released next week (Tuesday at 4:30pm as I recall) on how we handled that.

 

[TuxDave]

Originally posted by: pm

Originally posted by: MrDudeMan
lwhy do processors reduce in size? why not keep it the same size and continue implementing new features and technology? i am starting to learn about semi-advanced electronics at school now, so i am beginning to wonder about these things...

Aside from the things that Matthias wrote - which were all correct - they are actually slowly getting bigger. I have been working on Montecito - an upcoming member of the Itanium processor family. It has 1.75 billion transistors and the die size is the largest that I am aware of.

The problem with increasing die size is everything matthias mentioned as well as yield and power. You can only cool so many watts coming off of a chip - and each transistor will leak a certain amount of power (an amount that is increasing with each generation of process technology...) so if you increase your transistor count by 30% than you are also increasing the amount of power that is consumed by leakage by an equivalent amount, which hurts your overall power budget for the processor.

Yield is probably the primary concern. Imagine that you are scattering about 50 grains of sand over a 12" wafer. Each grain symbolizes a flaw - a bit of dust, a bubble in the photoresist, something. Now if you had one chip the size of the wafer (which isn't possible, but for the sake of arguement)... you'd have 50 errors on that chip and you would have zero yield on the wafer. You would pretty much never ever get a working chip. Now imagine that you have 50 chips on the wafer... well, each time it's likely that those grains of sand fall on the wafer that a few of the chips would somehow manage to avoid having one... and if you had 500, then you'd have 450 working chips... or even more. So clearly there is a huge benefit to he bottom line of the company in having the chip be fairly small... not only can you get more per wafer, but more are likely to work. The numbers are made up, but the analogy is close enough to real life.

Why is Montecito so huge? Most of the chip is cache - in excess of 24MB of cache - and there are mechanisms in place to replace bad cache lines... so if an error shows up in the cache, it can be fixed. And for power, well, there will be a lot of details released next week (Tuesday at 4:30pm as I recall) on how we handled that.

Go Intel!

<---- Fellow engineer in Intel DPG (or DEG now)

 

[Gibsons]

in excess of 24MB of cache

:Q

 

[Kasper4christ]

wow

 

[Calin]

You can not accelerate a processor's speed indefinitely by making it larger (with more transistors). The programs that are run are simply not written to take advantage of massive parallelism.
If you would have a VLIW (or EPIC) instruction set that contains 64 instructions in its 1024 bytes "instruction group" (or word, if you like) you could have a simple core capable of running one 16 bytes instruction per clock. You could make it work 64 times faster by using 64 simple cores in a single "processor". However, if you will make a single "processor" with 256 cores, the speed won't increase much (if at all) from the 64 cores processor.
Think at the x86 instruction set as prefering a single instruction. This is the reason increased complexity in x86 cores start to give out less and less of a total speed increase. This is the reason the execution units in the x86 processors remains at a (somewhat low) number - adding more execution units will simply use them less time.

 

[pm]

Originally posted by: TuxDave
Go Intel!

There are six Montecito papers being presented next week at ISSCC- we tied with IBM's Cell processor. We are all headed out tonight. I'm paper 16.1... and I'm nervously excited.

 

[CTho9305]

Originally posted by: pm

Originally posted by: TuxDave
Go Intel!

There are six Montecito papers being presented next week at ISSCC- we tied with IBM's Cell processor. We are all headed out tonight. I'm paper 16.1... and I'm nervously excited.

Good to see you still post here sometimes .

 

[SuperTool]

Some companies (Sun, Intel, HP, AMD, IBM that I am aware of) are using the real estate to put many copies of a core on a single die to make a multiprocessor on a chip. Sun's upcoming Niagara chip is a good example of puting many cores on one die:
http://news.zdnet.co.uk/0,39020330,39186690,00.htm

A new chip approach
Niagara will be the first major debut of a technology called chip multithreading (CMT), which is designed to let processors work more efficiently. With this approach, multiple computing engines called processor cores are combined on the same chip, and each core can juggle multiple instruction sequences called threads.

Today's processors spend much of their time waiting to retrieve data from memory. When Sun chips run into that problem, a new thread takes over while the first waits for data. Niagara, with eight cores each able to run four threads, can run a total of 32 threads in parallel.

Today's software will work on CMT chips, but must be optimised to work well, Yen said. "For example, internally in our system software, there are places where we may have limited the parallelism only to four simultaneous threads or eight," he said. "Now, knowing that even one processor can support 32 simultaneous threads, certainly we'd like to further enhance the parallelism."

Multiprocessor servers are Sun's core business, so it makes sense for them to design chips like that. It wouldn't make sense for Intel to put 8 P4 chips on one core, because the average P4 customer is not going to know what to do with 8 cores, the area of the chip would be huge due to a larger core, and the heatsink would resemble this But it will P4 should be faster for single thread performance, whichis it's core market.

But replicating same elements, either cores or cache is a good way of using the area, that some companies are choosing to do, because you can design a small area of the chip, and replicate it, which reduces your R&D cost compared to filling the area with unique elements.

 

[SuperTool]

Originally posted by: pm

Originally posted by: TuxDave
Go Intel!

There are six Montecito papers being presented next week at ISSCC- we tied with IBM's Cell processor. We are all headed out tonight. I'm paper 16.1... and I'm nervously excited.

16.1 Clock Distribution on a Dual-core
Multi-threaded Itanium®-Family Processor
1:30 PM
E. Fetzer1, P. Mahoney2, B. Doyle1, S. Naffziger1
1Hewlett Packard, Fort Collins, CO
2Intel, Fort Collins, CO
Clock distribution on the 90nm Itanium® processor is detailed. A
region-based active de-skew system reduces the PVT sources of skew
across the entire die during normal operation. Clock vernier devices
inserted at each local clock buffer allow up to a 10% clock-cycle
adjustment via firmware or scan. The system supports a constantly
varying frequency and consumes <25W from PLL to latch while providing
<10ps of skew across PVT.

10ps PVT skew is very impressive for such a huge chip. We are in the presence of greatness

 

[pm]

Originally posted by: SuperTool
10ps PVT skew is very impressive for such a huge chip. We are in the presence of greatness

Yeah, well, there's a caveat to that number. It's really 22ps and we don't clock the cache (L2 is asynchronous) so it's not quite as big a chip to clock as it appears. But those caveats aside, we are quoting true measured values and that really is PV and T. Most people don't factor temperature (T) in their numbers by taking their measurements at a quiescent state (or use calculated values). Our V is variable too - with Foxton our voltage goes all over the place during normal operation.

I don't know anything about greatness. I am feeling woefully intimidated at this conference and it hasn't even started yet.

Patrick Mahoney
Intel Corp.
Fort Collins, CO

 

[SuperTool]

Originally posted by: pm

Originally posted by: SuperTool
10ps PVT skew is very impressive for such a huge chip. We are in the presence of greatness

Yeah, well, there's a caveat to that number. It's really 22ps and we don't clock the cache (L2 is asynchronous) so it's not quite as big a chip to clock as it appears. But those caveats aside, we are quoting true measured values and that really is PV and T. Most people don't factor temperature (T) in their numbers by taking their measurements at a quiescent state (or use calculated values). Our V is variable too - with Foxton our voltage goes all over the place during normal operation.

I don't know anything about greatness. I am feeling woefully intimidated at this conference and it hasn't even started yet.

Patrick Mahoney
Intel Corp.
Fort Collins, CO

It seems like everytime Intel posts some ridiculously low skew number, there is a bunch of caveats attached
Is Intel and HP in Fort Collins a combined group or are they in different locations?

 

[pm]

Originally posted by: SuperToolIt seems like everytime Intel posts some ridiculously low skew number, there is a bunch of caveats attached
Is Intel and HP in Fort Collins a combined group or are they in different locations?

There's skew to the latches - which it seems to me is the "real" number - and that's 22ps. And then there's the skew of the primary clock route - and that's 10ps.

When people in the industry talk about clock skew, they talk about the skew of the routed tree, not the last part of the route which is to the latches themselves - mainly because the majority of the skew of the last part of the route is caused by routing limitations and is deterministic and can be factored into the timing tools whereas the skew of the grid is generally indeterministic (no one is quite sure what it will be at a certain point due to PVT - which is short for Process/Voltage/Temperature uncertainty - meaning that process variations, and localized and system-wide voltage variation, and then temperature variation across the die and depending on the workload). So in my mind, the real clock skew is the skew of the clock at the latches... but in reality almost everyone quotes PVT skew of the grid itself. And to be honest, the grid number is the important number... if you can factor in the skew into the tools, then it's not really real skew.

So anyway, there's the caveat... 10ps if you quote it using industry terminalogy - 22ps if you want the total system skew number.

As far as our formerly-HP colleagues.... we all one team at Intel now. Here is a link to one of the better articles about it.

 

[SuperTool]

Originally posted by: pm

Originally posted by: SuperToolIt seems like everytime Intel posts some ridiculously low skew number, there is a bunch of caveats attached
Is Intel and HP in Fort Collins a combined group or are they in different locations?

There's skew to the latches - which it seems to me is the "real" number - and that's 22ps. And then there's the skew of the primary clock route - and that's 10ps.

When people in the industry talk about clock skew, they talk about the skew of the routed tree, not the last part of the route which is to the latches themselves - mainly because the majority of the skew of the last part of the route is caused by routing limitations and is deterministic and can be factored into the timing tools whereas the skew of the grid is generally indeterministic (no one is quite sure what it will be at a certain point due to PVT - which is short for Process/Voltage/Temperature uncertainty - meaning that process variations, and localized and system-wide voltage variation, and then temperature variation across the die and depending on the workload). So in my mind, the real clock skew is the skew of the clock at the latches... but in reality almost everyone quotes PVT skew of the grid itself. And to be honest, the grid number is the important number... if you can factor in the skew into the tools, then it's not really real skew.

So anyway, there's the caveat... 10ps if you quote it using industry terminalogy - 22ps if you want the total system skew number.

As far as our formerly-HP colleagues.... we all one team at Intel now. Here is a link to one of the better articles about it.

So 10ps is the PVT portion of the skew that goes on top of whatever structural skew there is due to clock tree imbalances, and other deterministic things like that?

 

[stevty2889]

Originally posted by: pm
Why is Montecito so huge? Most of the chip is cache - in excess of 24MB of cache - and there are mechanisms in place to replace bad cache lines... so if an error shows up in the cache, it can be fixed. And for power, well, there will be a lot of details released next week (Tuesday at 4:30pm as I recall) on how we handled that.

24MB of cache?!? is that lvl 3 or lvl 2? Thats gotta produce a lot of heat...speaking of heat, is it possible to disable the thermal throttling on a lga775 prescott? I have 3.4ghz D0 stepping and can't keep the load temp under 70c, so the throttling is always kicking in..would isolating the PROCHOT# signal disable the throttling or would it force it to stay on constantly?