processor size, features, and speed...why do they limit themselves?

[TuxDave]

Originally posted by: stevty2889

Originally posted by: pm
Why is Montecito so huge? Most of the chip is cache - in excess of 24MB of cache - and there are mechanisms in place to replace bad cache lines... so if an error shows up in the cache, it can be fixed. And for power, well, there will be a lot of details released next week (Tuesday at 4:30pm as I recall) on how we handled that.

24MB of cache?!? is that lvl 3 or lvl 2? Thats gotta produce a lot of heat...speaking of heat, is it possible to disable the thermal throttling on a lga775 prescott? I have 3.4ghz D0 stepping and can't keep the load temp under 70c, so the throttling is always kicking in..would isolating the PROCHOT# signal disable the throttling or would it force it to stay on constantly?

I always thought cache was the 'cold' part of the processor.

 

[BEL6772]

Originally posted by: TuxDave

I always thought cache was the 'cold' part of the processor.

The cache has the highest concentration of transistors on the chip and it has to be constantly drawing power in order to maintain its data state.

 

[Sohcan]

Originally posted by: BEL6772

Originally posted by: TuxDave

I always thought cache was the 'cold' part of the processor.

The cache has the highest concentration of transistors on the chip and it has to be constantly drawing power in order to maintain its data state.

Actually, the power density of the L3 cache in Montecito is extremely low...the 24 MB L3 consumes less than 5% of the total chip power (4.2 Watts). There are large opportunities for power reduction in higher-level caches using architecture and circuit techniques.

Just so that Patrick doesn't get all the attention (), my team is also presenting at ISSCC tomorrow. Go Foxton!

16.7 Power and Temperature Control on a 90nm Itanium®-Family Processor

C. Poirier, R. McGowen, C. Bostak, S. Naffziger

This paper describes the embedded feedback and control system on a
90nm Itanium®-family processor, code-named Montecito, that
maximizes performance while staying within a target power and
temperature (PT) envelope. This system utilizes on-chip sensors and an
embedded micro-controller to measure PT and modulate voltage and
frequency to meet PT constraints.

 

[CTho9305]

Originally posted by: Sohcan

Originally posted by: BEL6772

Originally posted by: TuxDave

I always thought cache was the 'cold' part of the processor.

The cache has the highest concentration of transistors on the chip and it has to be constantly drawing power in order to maintain its data state.

Actually, the power density of the L3 cache in Montecito is extremely low...the 24 MB L3 consumes less than 5% of the total chip power (4.2 Watts). There are large opportunities for power reduction in higher-level caches using architecture and circuit techniques.

Just so that Patrick doesn't get all the attention (), my team is also presenting at ISSCC tomorrow. Go Foxton!

16.7 Power and Temperature Control on a 90nm Itanium®-Family Processor

C. Poirier, R. McGowen, C. Bostak, S. Naffziger

This paper describes the embedded feedback and control system on a
90nm Itanium®-family processor, code-named Montecito, that
maximizes performance while staying within a target power and
temperature (PT) envelope. This system utilizes on-chip sensors and an
embedded micro-controller to measure PT and modulate voltage and
frequency to meet PT constraints.

WISC-SP01 to Montecito in 3.5 years? Not bad

 

[SuperTool]

Originally posted by: BEL6772

Originally posted by: TuxDave

I always thought cache was the 'cold' part of the processor.

The cache has the highest concentration of transistors on the chip and it has to be constantly drawing power in order to maintain its data state.

You may be thinking about DRAM. SRAM does not need to be refreshed to maintain its state.
But even with refreshing, I don't think DRAMs have anywhere near the power densities of logic units.

 

[BEL6772]

Originally posted by: SuperTool

Originally posted by: BEL6772

Originally posted by: TuxDave

I always thought cache was the 'cold' part of the processor.

The cache has the highest concentration of transistors on the chip and it has to be constantly drawing power in order to maintain its data state.

You may be thinking about DRAM. SRAM does not need to be refreshed to maintain its state.
But even with refreshing, I don't think DRAMs have anywhere near the power densities of logic units.

I guess I was confused. SRAM is basically a pair of inverters connected to feed back to each other, right? If Vcc is removed, the state goes away, right? I know that you can lower Vcc to sections and put them to 'sleep', but they do have to be constantly powered to maintain state, right? I've also heard that SRAM cells are highly optimized for space, making them among the densest structures on CPUs.

From those tidbits I concluded (incorrectly) that having a lot of transistors, densly packed, all drawing some level of current, would make for a fairly warm bit of silicon.

Of course, the 2x clock section of the pipeline probably keeps pretty warm, too!

 

[itachi]

basically, yea.. it's a pair of inverters controlled by a pair of pass-transistors.. cmos has no collector, vDD not vCC.. but yea, if you remove the power it'll lose it's state. but dram doesn't refresh itself by keeping the power on.. it has to read and rewrite every single value within it's cycle time.. and when the value is read from a cell it loses it's charge.. so it has to be refreshed again. with the power on, it'll lose it's value over time.. sram on the otherhand keeps its value so long as the power is on.

 

[TuxDave]

Originally posted by: itachi
basically, yea.. it's a pair of inverters controlled by a pair of pass-transistors.. cmos has no collector, vDD not vCC.. but yea, if you remove the power it'll lose it's state. but dram doesn't refresh itself by keeping the power on.. it has to read and rewrite every single value within it's cycle time.. and when the value is read from a cell it loses it's charge.. so it has to be refreshed again. with the power on, it'll lose it's value over time.. sram on the otherhand keeps its value so long as the power is on.

Yes but the power usage in SRAM cells are dominated by leakage and not active switching like what you would see in a high speed execution unit. If you have clever ways to reduce leakage, then SRAM power ain't that bad at all.

 

[Sunner]

This has got to be the best post in AT for a long long time, good to see you're still around pm and Sochan

 

[IntelUser2000]

"Of course, the 2x clock section of the pipeline probably keeps pretty warm, too!"

Anandtech's article on that mentioned about the double pumped ALUs and its power consumption/heat. They said its one of the coolest running parts of the CPU due to the technology used called Low Voltage Differential Swing.


What is clock skew? I have learned electronics but I am not in computer related electronics. I heard that clock skew has to do with how much the CPU will be able to clock?

 

[TuxDave]

Originally posted by: IntelUser2000
"Of course, the 2x clock section of the pipeline probably keeps pretty warm, too!"

Anandtech's article on that mentioned about the double pumped ALUs and its power consumption/heat. They said its one of the coolest running parts of the CPU due to the technology used called Low Voltage Differential Swing.


What is clock skew? I have learned electronics but I am not in computer related electronics. I heard that clock skew has to do with how much the CPU will be able to clock?

In a nutshell, the clock signal doesn't arrive at to all latches/flops/registers/whatever at the same time. There is a systematic AND random variation which will cause the clock to arrive later or earlier to one point relative to another point. That difference is known as clock skew.

 

[pm]

There's a great Stanford lecture by Intel's Ian Young on clock distribution and clocking, if people are interested. Covers all aspects of clocking and is fairly straightforward and interesting for people who don't have a background in VLSI design - ie. I think people here will enjoy it.

http://www.stanford.edu/class/ee380/

(it's a streaming video, click on the little movie camera to start it. You'll probably want to skip the first 15 minutes or so of the EE380 background to get to the start of the talk).

 

[TuxDave]

Originally posted by: pm
There's a great Stanford lecture by Intel's Ian Young on clock distribution and clocking, if people are interested. Covers all aspects of clocking and is fairly straightforward and interesting for people who don't have a background in VLSI design - ie. I think people here will enjoy it.

http://www.stanford.edu/class/ee380/

(it's a streaming video, click on the little movie camera to start it. You'll probably want to skip the first 15 minutes or so of the EE380 background to get to the start of the talk).

Thanks for the link even though it IS only Stanfuuurd. Go Cal!

 

[pm]

It's funny, Ian Young says almost the exact same thing at the start of the talk.