NASA publishes first 3rd party benches of Apple G5 machine vs. P4.

[Eug]

An Evaluation of PowerMac G5 Systems for Computational Fluid Dynamics Applications. (And here is the PDF.)

Basically, with this fluid dynamics benchmark, a G5 2.0 GHz (single CPU) performs on par with a Pentium 4 2.66. The G4 isn't even in the running of course. The conclusion is as follows:

The primary purpose of this test was to determine how G5 scalar floating point performance compares to G4 performance in CFD applications. As a secondary part of this test, G4 and G5 benchmark results were compared to similar results obtained on Pentium 4 systems. Overall, the scalar floating point performance of G5 systems is much improved over G4 systems due to better per clock cycle efficiency combined with higher clock speeds. Based on preliminary testing with an existing version of Jet3D (not recompiled or optimized for the G5), it appears that the G5 has about 22% better scalar floating point performance per clock cycle than the G4 systems tested and 32% better floating point performance per clock cycle than the P4 systems tested. Based on raw scalar floating point performance in Jet3D, a 2GHz G5 system can match a 2.66GHz P4 system, and this is a dramatic improvement from earlier tests where G4 systems lagged behind higher clock speed P4 systems. Based on an extrapolation of current P4 results, the 2GHz G5 would lag newly announced 3.2GHz P4 systems in Jet3D scalar floating point performance by about 20%, but this kind of comparison is best deferred until G5-aware compiler tools become available (since a 20% performance gain is well within the potential of compiler optimization).

Vector performance of the G5 remains excellent, and is inline with current G4 systems on a per clock cycle basis. As a result, raw vector performance of the G5 will be boosted simply by its higher clock speeds relative to current G4 systems.

Finally, it is important to note that the current test does not factor machine cost or intended use into the picture, and that can have a large impact, especially in clustering applications.

Pentium 4 2.66 GHz - 255 MFLOPS
Pentium 4 2.0 GHz - 192
Xserve G4 1.0 GHz - 105
Power Mac G4 1.25 GHz - 129
Power Mac G5 2.0 GHz - 254
Power Mac G5 2.0 GHz Dual - 498

Judging by these benches, for non-bandwidth intensive apps a dual 2.0 G5 would run at about the speed of a 2.66 dual Xeon. (The G5 may be faster if bandwidth is a limiting factor however, and I suspect that why the dual G5 did so well on Apple's bakeoffs. But that's a bus speed issue, not a CPU speed issue so much.)

 

[gf4200isdabest]

Nice link. Though it does look a bit hoaky being hosted at "members.cox.net"

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

 

[zephyrprime]

Shouldn't they be investigating a space shuttle crash or something and leave the benching to us?

 

[Eug]

It should keep the Apple Zealots down for a while. It won't, but it should.

Heheh, it's ironic you say that, because people here of late have taken to calling me an Apple zealot.

Anyways, originally I had predicted that a 1.8 GHz G5 would perform at about the speed of a 2.53 GHz P4, or perhaps a 2.3 GHz theoretical P4 with HyperThreading. (People now tell me that will single threaded benches, HT would weaken performance however.) So with my prediction, a 2.0 GHz PPC 970 should should have been in the range of a 2.8 GHz non-HT Xeon. 2.66 GHz P4 (533 MHz bus) is close enough I guess.

For bandwidth limited apps, however, the G5 would likely still be much faster. The dual Xeon 2.66 (and dual Xeon 3.06 for that matter) is on a single 533 MHz bus, whereas the dual G5 2.0 is on a dual 1 GHz. bus. This is probably how Apple's tests were "rigged".

Shouldn't they be investigating a space shuttle crash or something and leave the benching to us?

LOL. I'd imagine fluid dynamics might be interesting for them. I'd hope they're not buying their computers based on QIII numbers.

 

[Markfw]

Not to get off topic, but while we have P4 and Apple benches, why not an Opteron dual setup bench ? They are setup to run against Xenons, and the last benches I saw at 1.8 ghz, kicked the Xeon's butt.

 

[EdipisReks]

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

 

[Eug]

Originally posted by: Markfw900
Not to get off topic, but while we have P4 and Apple benches, why not an Opteron dual setup bench ? They are setup to run against Xenons, and the last benches I saw at 1.8 ghz, kicked the Xeon's butt.

I dunno, ask NASA.

 

[NFS4]

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

 

[Markfw]

Here are some NASA benches, and this is where they kicked the Xeon:
NASA benches of Xeon and Opteron

 

[EdipisReks]

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

i think i'm going to quit coming to this forum. the level of ignorance about how computers, compilers, and software benchmarks work is astouding.

 

[AnImuS]

Originally posted by: Markfw900
Not to get off topic, but while we have P4 and Apple benches, why not an Opteron dual setup bench ? They are setup to run against Xenons, and the last benches I saw at 1.8 ghz, kicked the Xeon's butt.

Because the dual G5 cant keep up with opterons at 1.8GHZ.
Else apple would of put them in the "were faster" benchmarks...

 

[Eug]

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house"

Actually, I wouldn't agree with the second part of the second sentence. A 3.2 GHz P4 would be VERY fast, but I'm not sure the 800 MHz would make much difference here, because the memory path is not stressed. It sounds like this is purely a CPU benchmark.

Indeed, one might expect a dual G5 to "clean house" with a very memory bandwidth intensive app, since the G5 sports dual 1 GHz bus. In fact, I wouldn't be surprised if a single G5 2.0 beat a single 800 MHz P4 3.2 in these types of apps.

In other words:
P4 3.2 wins for raw CPU output.
G5 2.0 wins for memory intensive apps.

 

[NFS4]

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

i think i'm going to quit coming to this forum. the level of ignorance about how computers, compilers, and software benchmarks work is astouding.

And how is this any different than Apple benching the Pentium 4 without using an Intel based compiler for their "comprehensive" benchmarks?

 

[EdipisReks]

Originally posted by: AnImuS

Originally posted by: Markfw900
Not to get off topic, but while we have P4 and Apple benches, why not an Opteron dual setup bench ? They are setup to run against Xenons, and the last benches I saw at 1.8 ghz, kicked the Xeon's butt.

Because the dual G5 cant keep up with opterons at 1.8GHZ.
Else apple would of put them in the "were faster" benchmarks...

i quit.

 

[NFS4]

Indeed, one might expect a dual G5 to "clean house" with a very memory bandwidth intensive app, since the G5 sports dual 1 GHz bus. In fact, I wouldn't be surprised if a single G5 2.0 beat a single 800 MHz P4 3.2 in these types of apps.

The system bus is at 1GHz, but what's the DDR memory bandwidth on the G5's?

 

[EdipisReks]

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

i think i'm going to quit coming to this forum. the level of ignorance about how computers, compilers, and software benchmarks work is astouding.

And how is this any different than Apple benching the Pentium 4 without using an Intel based compiler for their "comprehensive" benchmarks?

lets see. hmmm. on the Apple test, both the Apple machine and the Intel machine were equally optimized for using a common system open source compiler. on this test, the Intel machine is optimized for, and the Apple machine wasn't. hmmmm, i can't see a difference there, no sir.

hell, in the conclusion of the test, the tester said that comparing the G5 to the top of the line 3.2 right now isn't fair, since G5 aware compilers haven't been released yet.

 

[EdipisReks]

Originally posted by: NFS4

Indeed, one might expect a dual G5 to "clean house" with a very memory bandwidth intensive app, since the G5 sports dual 1 GHz bus. In fact, I wouldn't be surprised if a single G5 2.0 beat a single 800 MHz P4 3.2 in these types of apps.

The system bus is at 1GHz, but what's the DDR memory bandwidth on the G5's?

google is your friend.

 

[Eug]

Originally posted by: NFS4

Indeed, one might expect a dual G5 to "clean house" with a very memory bandwidth intensive app, since the G5 sports dual 1 GHz bus. In fact, I wouldn't be surprised if a single G5 2.0 beat a single 800 MHz P4 3.2 in these types of apps.

The system bus is at 1GHz, but what's the DDR memory bandwidth on the G5's?

The memory bandwidth per se is the same as the P4 (dual channel DDR400), but the connection of the CPU to system controller is via two independent 1 GHz busses for the dual 2.0, and one 1 GHz for the single 2.0 (which doesn't exist unless you rip out a CPU).

In other words, for apps shuffling around a lot of data, the G5 should still be faster (at least in certain situations), despite having the same dual channel DDR400 memory bus.

But as you've pointed out, in CPU-bound tasks, the P4 would win compared to a single G5.

 

[NFS4]

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

i think i'm going to quit coming to this forum. the level of ignorance about how computers, compilers, and software benchmarks work is astouding.

And how is this any different than Apple benching the Pentium 4 without using an Intel based compiler for their "comprehensive" benchmarks?

lets see. hmmm. on the Apple test, both the Apple machine and the Intel machine were equally optimized for using a common system open source compiler. on this test, the Intel machine is optimized for, and the Apple machine wasn't. hmmmm, i can't see a difference there, no sir.

hell, in the conclusion of the test, the tester said that comparing the G5 to the top of the line 3.2 right now isn't fair, since G5 aware compilers haven't been released yet.

Hmm, let's see:

Before we examine the SPEC results that Apple/Veritest claims, it must be noted that Apple/Veritest have used a few "cheats" to make the G5 look better. So whenever you see a Apple/Veritest result in the following tables, be aware that it has been affected by the following "cheats".

Apple/Veritest used a special fast malloc library on the G5 benchmark, but did not use it on the Dell/Intel benchmark, thus giving the G5 an unfair advantage. Here is the relevant quote from the Veritest report:


"Installed a high performance, single threaded malloc library. This library implementation is geared for speed rather than memory efficiency and is single-threaded which makes it unsuitable for many uses. Special provisions are made for very small allocations (less than 4 bytes)."
(Page 5, also see Appendix E, Page 26, Veritest PDF)

http://www.haxial.com/spls-soapbox/apple-powermac-G5/

 

[EdipisReks]

what irritates me about the responses from people on this thread is that nobody seems to remember anything. when the Pentium IV came out, it got thumped because nothing had been recompiled for it. of course, 3 years later with multiple revisions and total industry support, the PIV is the fastest desktop x86 processor. the G5 has not quite come out yet, and there is no optimization for it at a software level. however, this non supported, first revision chip is far from being thumped, and will only get better and better. if the PIV started out a dog and ended up prom queen, what do you think the G5 is gonna do when it starts out rather nice and is backed by both IBM and Apple who want the speeds to increase as quickly as possible?

 

[EdipisReks]

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: NFS4

Originally posted by: EdipisReks

Originally posted by: gf4200isdabest

Either way, it doesn't surprise me much. It should keep the Apple Zealots down for a while. It won't, but it should.

that's moronic. by your reasoning, the Athlon XP 3200+ being faster in one benchmark than a 3200C PIV should keep the Intel zealots down. also, as is mentioned, this benchmark was done with non G5 aware compilers. the fact that that the G5 did so well in a non optimized test against a PIV, which the test was optimized for, shows how powerful the G5 is. the PIV sure as heck didn't do this well when it first came out and nothing was optimized for it. it didn't become competive until PIV optimized compilers came out. the G5 isn't suffering from the same problem.

That was only a 2.66GHz P4. A 3.2GHz, 800MHz P4 would definitely "clean house" Or let's not even forget about the soon to be released Prescotts with 1MB L2 cache.

Move along, nothing to see here

i think i'm going to quit coming to this forum. the level of ignorance about how computers, compilers, and software benchmarks work is astouding.

And how is this any different than Apple benching the Pentium 4 without using an Intel based compiler for their "comprehensive" benchmarks?

lets see. hmmm. on the Apple test, both the Apple machine and the Intel machine were equally optimized for using a common system open source compiler. on this test, the Intel machine is optimized for, and the Apple machine wasn't. hmmmm, i can't see a difference there, no sir.

hell, in the conclusion of the test, the tester said that comparing the G5 to the top of the line 3.2 right now isn't fair, since G5 aware compilers haven't been released yet.

Hmm, let's see:

Before we examine the SPEC results that Apple/Veritest claims, it must be noted that Apple/Veritest have used a few "cheats" to make the G5 look better. So whenever you see a Apple/Veritest result in the following tables, be aware that it has been affected by the following "cheats".

Apple/Veritest used a special fast malloc library on the G5 benchmark, but did not use it on the Dell/Intel benchmark, thus giving the G5 an unfair advantage. Here is the relevant quote from the Veritest report:


"Installed a high performance, single threaded malloc library. This library implementation is geared for speed rather than memory efficiency and is single-threaded which makes it unsuitable for many uses. Special provisions are made for very small allocations (less than 4 bytes)."
(Page 5, also see Appendix E, Page 26, Veritest PDF)

http://www.haxial.com/spls-soapbox/apple-powermac-G5/

i wish this forum had the tard emoticon. anyone who brings out that blog is advertising their complete ignorance on this subject.

 

[GL]

This is much better than I had anticipated. Once a G5-aware compiler comes out, it could very well be neck-to-neck with a 3.2 GHz P4. And let's not forget there's another CPU there in that G5 system...The dual G5 system scored 498 MFLOPS to the single P4's 255 in the scalar benchmark. That's pretty damn impressive. I'm actually more impressed now, than I was when Apple did the WWDC bakeoff.

 

[EdipisReks]

Originally posted by: GL
This is much better than I had anticipated. Once a G5-aware compiler comes out, it could very well be neck-to-neck with a 3.2 GHz P4. And let's not forget there's another CPU there in that G5 system...The dual G5 system scored 498 MFLOPS to the single P4's 255 in the scalar benchmark. That's pretty damn impressive. I'm actually more impressed now, than I was when Apple did the WWDC bakeoff.

wow, somebody has a clue. must be the end of the world.

 

[Pariah]

Originally posted by: EdipisReks
what irritates me about the responses from people on this thread is that nobody seems to remember anything. when the Pentium IV came out, it got thumped because nothing had been recompiled for it. of course, 3 years later with multiple revisions and total industry support, the PIV is the fastest desktop x86 processor. the G5 has not quite come out yet, and there is no optimization for it at a software level. however, this non supported, first revision chip is far from being thumped, and will only get better and better. if the PIV started out a dog and ended up prom queen, what do you think the G5 is gonna do when it starts out rather nice and is backed by both IBM and Apple who want the speeds to increase as quickly as possible?

Uhh, no. The P4 wa designed with high clock speeds in mind with lower IPC. When it was released the clock speeds weren't high enough to overcome the lower IPC. If you ran today's software with first generation P4's, they wouldn't be any faster now than they were then. They stunk then, they still stink now.

 

[Eug]

Edipis, Take a deep breath in...

NFS4, The Haxial "expose" has been repeatedly discredited around the net. One good place to look is in the Ars forums. The consensus is that 1) He didn't read the VeriTest article correctly & 2) He doesn't know what he's talking about anyway.

There ARE issues about Apple's testing methodology, but it has more to do with the fact that GCC was used and not ICC for the Dell tests. Not that it would likely have mattered a huge amount though, since the tests that Apple chose to highlight (like Luxology's demo and Mathematica) likely depend a lot on the bus architecture I'm guessing. (By the way, it would seem that Luxology did not use ICC either. Dunno how the Mathematica demo was coded/compiled.)