Originally posted by: taltamir
Sony sells defective cpus now? doesn't surprise me one bit, sony's motto should be "we hate you"
Article.
The Cell processor is so complex that IBM even accepts chips that have only four out of the eight cores working. Not all cores end up functional says Reeves. In regards to why the yields are so low, Reeves says "[defects becomes a bigger problem the bigger the chip is. With chips that are one-by-one and silicon germanium, we can get yields of 95 percent. With a chip like the Cell processor, you?re lucky to get 10 or 20 percent. If you put logic redundancy on it, you can double that." According to Reeves, Sony will be using Cell processors whether they have all cores functional or not. Reeves says that the PlayStation 3 requires at least seven of the eight cores operational.
According to Reeves, IBM is still debating whether or not to discard the processors that have only six or less cores operational. Because of the design, the processors are still operational and can be used for various applications. IBM says that it will reserve the top chips for applications such as medical imaging and defense applications.
Originally posted by: NanoStuff
First off, you're measuring failure rate as a function of the number of cores. Defect probability is a function of, usually, the sum of transistors. Also, you suggest that two cores will necessarily be grouped into a single die, which, as SLI shows, does not have to be.
Lets just simplify here.
1000x 1 Billion transistor die. 10% failure rate, 900 working cores.
> 900 Billion working transistors.
4000x 250 Million transistor die. 2.5% failure rate, 3900 working cores.
> 975 Billion working transistors.
Quarter complexity, quarter failure rate, lower sum of transistors lost per core. Everyone wins.
I think the OP was referring to using multiple core GPUs on a single card
as contrasted with the current scheme of using single-core GPUs and then either speeding them up or adding an extra GPU on its own graphics card (SLI, Crossfire). Or the multiple-GPU-on-a-single-card technique, which I don't think anyone uses. Either way, putting multiple cores close together at full clock speed on a single die allows for MUCH faster communication between them for a number of reasons...basically why your L1 cache is faster than L2, which is faster than system memory, even though all three are just an array of silicon transistors.
As for your numbers, I don't understand what you're getting at.
1 trillion transistors per wafer, 10% failure rate = 900 billion "working" transistors. Omitting the possibility of multiple defects on a single core (making this a pessimistic estimate), that's 900 "working" cores with a a complex single core.
Now it appears that you're postulating a 4-core system, with each core being a quarter as complex as the single-core system, to create a GPU that in
very rough terms is close to the original in speed. My scenario doubled-up the single-core chip to create the multi-core...in other words, we were getting a lower yield of a faster GPU. I think this was part of the disagreement.
I don't know why you're postulating that the failure rate is somehow lower now...there ought to be just as many critical defects per wafer, regardless of whether we are using it to create a vast quantity of simple PNP transistors, or making a mythical wafer-large die for some imaginary computer. The difference is that the critical defect can be ANYWHERE on the wafer-large die to render it inoperable, whereas we'll have a whole bunch of transistors there were "missed" by the defect and therefore usable.
Now, if there was a way to create a whole bunch of very simple cores, and then link them together as if they had been created on a single die with no performance hit, you'd get a much higher yield from creating simpler cores. But this isn't how it works...AMD, Intel, and IBM all create multiple cores on a single die, so that a single defected core will render the whole dual-core chip inoperable (or at the very least second-tier goods; not suitable for the enthusiast market). Thus, in your scheme of using 4 cores of 1/4 complexity, we should see EXACTLY the same reject rate as the single core of normal complexity.
What I do not know is whether the addition of transistors necessary for intercommunication between the cores is greater than or less than the reduction of transistors due to any shared resources between the cores.
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