Discussion Microarchitecture Comparison Chart

[Cardyak]

I’ve been slowly compiling a Microarchitecture Comparison Chart over the past few months. The purpose of this to estimate the IPC of different architectures and allow people to at least make a comparison between different architecture designs.

I understand there are inherent limitations with such an endeavour:

• IPC varies with different workloads and is inconsistent
• IPC varies for each individual SKU within an architecture due to differences such as memory speed support and cache sizes
• IPC varies with clock speed
• SMT yields are difficult to calculate and inconsistent in their performance enhancement

Various members of this forum have been castigated for attempting comparisons like this in the past, however that doesn’t mean we should stop attempting to compare architectures to each other, just that these salient points should be kept in mind when doing so.

Hence, today I am taking the (maybe) naive decision to share this comparison chart with the wider AnandTech Community. I’ve also included links to my Microarchitecture Block Diagram Repository which you can find by clicking on the links in the Codename column.

I’ve even attempted to include Apple’s architectures as well (Despite the dearth of transparent information)

Microarchitecture Comparison Chart can be located here: https://docs.google.com/spreadsheet...B9oLbTJCFwx0iFI-vUs6WFyuE/edit#gid=1076260513

Microarchitecture Block Diagram Repository: https://drive.google.com/drive/folders/1W4CIRKtNML74BKjSbXerRsIzAUk3ppSG

More info can be found on my Twitter here: https://twitter.com/Cardyak

Extra Credit should also go to David Kanter and David Schor for providing extra information and pointers.

 

[amrnuke]

For IPC is the formula and benchmarks used going to be shared?

 

[name99]

The basic numbers are nice to have, but as I keep saying even more important are the ALGORITHMS used by the CPU. What are the branch prediction algorithms, the cache replacement algorithms. Something as basic is: is a cache maintained of structures encountered during a page walk, and if so of what form? Or, is fetch address prediction decoupled from actual fetch?

Yes, it's hard to find these details. But they are sometimes listed in the public presentations, or they come to light in successive user investigations.
I'd say, at the very least, start writing down (with references) what you learn for each core and that may encourage others to help you fill in details.

 

[moinmoin]

Want to second amrnuke's question.

Aside that it looks good. Though I'd recommend not to use Intel's PR name hyperthreading for non-Intel products or as a general title. The correct term there is SMT (simultaneous multithreading, compare to clustered multithreading/CMT you already use).

Also great work on all those block diagrams!

 

[Zepp]

Nice work, I like these kind of charts.

which core is being used for 'bulldozer'? zambezi? bristol?

It would be nice to see the progression of IPC in the CON cores. As I recall Excavator was some 20-25% higher than the original bulldozer core.

 

[SarahKerrigan]

Nice. Any chance you can add Power? I can provide whatever performance info for P8 and P9 you'd need, including SPEC2017 run output.

Also, I noticed several cores with implementation-specific LLC size are listed with an LLC size included; what parts are you looking at for these?

I have questions about the "Single Threaded IPC" for A76 - that seems awfully low to me. I haven't spent much quality time with A76, but I have with N1 which is a closely related core, and for ST int code streams the N1 does tend to beat iso-clock Zen 2 by a few percent in my experience.

 

[Hulk]

Great job. Thanks for sharing this. How are you calculating IPC?

Also the charts are really excellent and so informative. You can flip through and instantly notice architecture changes. Well done.

I think you have the right amount of data in the chart. Once you start adding things which require more detail, (like power, which needs process details, etc...) you start to go down a rabbit hole.

Your spreadsheet and charts focus on architecture.

Really nice work! Thanks again!